NDLI: Silicon-hybrid wafer-scale integration achieved with multilevel aluminum interconnects

Content Provider	IEEE Xplore Digital Library
Author	Takahashi, G.L. Kolesar, E.S.
Copyright Year	1989
Description	Author affiliation: Sacramento Air Logistics Center, McClellan AFB, CA, USA (Takahashi, G.L.)
Abstract	A silicon-hybrid wafer-scale integration (WSI) technique has been developed to interconnect complementary metal-oxide semiconductor (CMOS) circuits. Electrical performance tests and processing diagnostics reveal that the interconnect design is very promising. The wafer-scale integrated circuit was fabricated by mounting two CMOS integrated circuit dies into etched wells and then planarizing the surface of the silicon wafer substrate. Next the wafer's surface was coated with a photosensitive polyimide and patterned with vias to accommodate the interconnecting conductors. The CMOS dies were two-bit shift registers and were electrically interconnected with aluminum conductors using conventional silicon processing techniques. A diagnostic evaluation was accomplished to determine the electrical continuity of the conductors and via contacts. When compared to a complementary wire-bonded interconnect scheme, the silicon WSI technology was found to be the superior performer at 1-MHz operating frequencies. Discontinuous interconnects were evaluated and the failures were identified to occur at the severe topographical steps encountered on the substrate wafer's surface.<>
Starting Page	17
Ending Page	23
File Size	657734
Page Count	7
File Format	PDF
DOI	10.1109/NAECON.1989.40185
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1989-05-22
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer scale integration Integrated circuit interconnections Surface topography Silicon Conductors CMOS integrated circuits Substrates MOS devices Circuit testing Etching
Content Type	Text
Resource Type	Article

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