NDLI: Formation and Reduction of Embedded Contamination Defects Detected after FEOL Poly Patterning

Content Provider	IEEE Xplore Digital Library
Author	Chienfan Yu Arndt, R. Ronsheim, P. St Lawrence, M. Hong Lin Zaitz, M. Colwill, B. Bruley, J. Crispo, G.
Copyright Year	2006
Description	Author affiliation: IBM Syst. & Tech. Group, East Fishkill, NY (Chienfan Yu; Arndt, R.; Ronsheim, P.; St Lawrence, M.; Hong Lin; Zaitz, M.; Colwill, B.; Bruley, J.)
Abstract	Embedded contamination (EC) is a significant contributor to front-end-of-line (FEOL) defects detected at poly conductor (PC) bright field (BF) PLY (process limited yield) inspection after poly patterning. There are two types of EC defects found in PC PLY after poly line formation. A small percentage of them has relatively larger size than ground rule and is believed to be related to particle residue incoming to or fallen during poly silicon deposition. The vast majority of the ECs are small and appear first at post poly deposition dark field (DF) PLY inspection as poly bumps. Subsequent PC lithographic pattering and plasma etch modification transform the poly bumps into ECs as detected in PC BF PLY. No appreciable correlation of these small bumps was found to any of the prior level partition BF PLY defects through the defect source analysis (DSA). Larger EC was found to be effectively removed with improved wet clean and the use of cryogenic aerosol clean prior to well anneal process. Small EC was found to be reduced by proper control and minimization of STI height and divot, as well as the processing procedure and environment change
Starting Page	206
Ending Page	210
File Size	672801
Page Count	5
File Format	PDF
ISBN	1424402549
ISSN	10788743
DOI	10.1109/ASMC.2006.4676216
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Contamination Inspection Conductors Silicon Plasma applications Plasma sources Etching Cryogenics Aerosols Annealing defect source analysis (DSA) embedded contamination trace metallic
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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