NDLI: Evaluation of the yield impact of epitaxial defects on advanced semiconductor technologies

Content Provider	IEEE Xplore Digital Library
Author	Williams, R. Jacques, R. Akbulut, M. Wayne Chen
Copyright Year	2000
Description	Author affiliation: Intel Corp., Rio Rancho, NM, USA (Williams, R.)
Abstract	Epitaxial defects (e.g., stacking faults, epi-spikes, mounds, hillocks, and pits) can often impact product yields, depending upon the type, size, and location of the defect, as well as the design and yield sensitivity of the respective semiconductor product devices. However, the overall yield impact from epitaxial defects has been difficult to assess since the defect sensitivity, capture rates, and classification for these defects has often been poor on product wafers. In a collaborative study between Intel Corporation and KLA-Tencor Corporation, the SP1/sup TBI/ defect inspection system was used to inspect and classify epitaxial wafers for an advanced semiconductor manufacturing process. After completion of the semiconductor processing, the defect kill rates and the yield impact were evaluated using bitmapping analysis. The project results demonstrate that the enhanced defect sensitivity and better capture rate of the SP1/sup TBI/ inspection system can provide a significant improvement in the defect inspection capabilities currently being utilized for epitaxial wafers. The SP1/sup TBI/ inspection system was also able to successfully classify particles and epitaxial defects using real-time defect classification (RTDC), with greater than 99 percent accuracy. The epitaxial defect levels and the corresponding product yield impact were observed to vary significantly between major silicon wafer suppliers. Consequently, these results can be useful in the development of tighter defect specifications for epitaxial wafers to minimize the resulting yield loss from epitaxial defects.
Starting Page	1
Ending Page	7
File Size	611013
Page Count	7
File Format	PDF
ISBN	0780359216
ISSN	10788743
DOI	10.1109/ASMC.2000.902550
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-09-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inspection Silicon Stacking Semiconductor films Crystallization Manufacturing processes Real time systems Collaboration CMOS technology Electronics industry
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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