NDLI: A mathematical model for defect impact based on in-line vs test data correlations

Content Provider	IEEE Xplore Digital Library
Author	Fernandez, A. Lorenzo, A. Cruceta, S. Oter, D. James, D.A.
Copyright Year	1999
Description	Author affiliation: Lucent Technol. Microelectron., Madrid, Spain (Fernandez, A.)
Abstract	This paper describes the methodology used to build a mathematical model to determine the yield impact of particles in integrated circuits, known as "Kill Ratio" (KR). The Kill Ratio represents the probability that a certain particle of a given size at a given inspection step will cause the failure of the device. These numbers are calculated based on actual particle data, collected on a routine basis inside the clean room, and the yield data after electrical test of finished product. The objective we pursue with a mathematical model is to find a simple expression for the Kill Ratio, based on defect sizes, which can be related to some geometrical characteristic of the device layout. While the procedure to calculate the Kill Ratio from particle and probe data is fundamentally statistical (that is, enough data must be collected to ensure the accuracy of these numbers), a mathematical expression based on design parameters would allow us to calculate the Kill Ratio of product with very low volume, such as prototypes, new products, technology qualification products, etc. This type of information will speed up the yield improvement cycle, as well as to the time to "yield entitlement" for the new products and technologies introduction. The paper gives the detail of the results obtained with this model and also some future plans for refining the model.
Starting Page	92
Ending Page	96
File Size	513963
Page Count	5
File Format	PDF
ISBN	0780352173
ISSN	10788743
DOI	10.1109/ASMC.1999.798189
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-09-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Mathematical model Inspection Circuit testing Integrated circuit technology Failure analysis Yield estimation Integrated circuit testing Integrated circuit yield Integrated circuit modeling Probes
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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