NDLI: Evaluating workcell layouts

Content Provider	IEEE Xplore Digital Library
Author	Nehme, D. McKiddie, R.
Copyright Year	1995
Description	Author affiliation: Pavilion Technol., Austin, TX, USA (Nehme, D.)
Abstract	Traditionally, the tools of a wafer fab are laid out into "farms" where tools that perform similar functions are located in one area. With a given process flow and farm layout, estimating material-movement metrics like number of interbay moves and total wafer travel distance is relatively straightforward. This is because there is a one-to-one correspondence between type of processing (etch, photo, etc.) and a given "farm" area. However, in a workcell or mixed farm-workcell layout, there is no such correspondence because similar tools are often located in different areas of the fab. In addition, these distributed tools often support multiple processing steps. Thus, it is a challenge for analysts to evaluate material movement metrics with workcell layouts because of the difficulty in assigning processing steps to particular tools. We present a simple linear programming model that, given the process flows, the start rates, and a fab layout, quickly performs this assignment. The model assigns steps to individual tools or to specific bays with the objective of minimizing wafer travel subject to tool capacity constraints. In performing this analysis, the modeling logic takes into account the fact that a lot of wafers will leave the same tool that it entered. This creates dependencies among assignments of process steps to tools. Linear programming is well suited to handle these types of dependencies. The model is intended for quick evaluations of layouts or given an existing layout, for assigning a processing flow to actual tools. In this paper we give an intuitive explanation of the model, and describe how we used it to evaluate the effect of different workcell designs on material movement.
Starting Page	111
Ending Page	114
File Size	315620
Page Count	4
File Format	PDF
ISBN	0780327136
ISSN	10788743
DOI	10.1109/ASMC.1995.484351
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-11-13
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Yield estimation Linear programming Etching Performance analysis Logic programming Thin films Costs Production facilities Manufacturing processes
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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