NDLI: Partitioning yield loss via test pattern structures and critical areas

Content Provider	IEEE Xplore Digital Library
Author	Evans, W.M. Cyr, R. Wilson, D.
Copyright Year	1995
Description	Author affiliation: Nat. Semicond. Corp., South Portland, ME, USA (Evans, W.M.; Cyr, R.; Wilson, D.)
Abstract	Yield loss detected at electrical test is attributable to various factors in the fabrication of semiconductor devices. The accurate partitioning of this yield loss to the appropriate tool or process segment is necessary for rapid yield improvements. In this paper we discuss a method of partitioning that uses production test patterns and associated critical areas. We discuss the calculation of critical area as used in this paper, as well as methods for determining relevant test pattern structures that relate to the product. This model relies on full loop test patterns designed to maximize the available information for micro yield modeling. This method has been used successfully in new product yield enhancement activities for bipolar products at NSFM. The partitioning starts with a division between systematic and random components as a result of wafer map analysis. We give an algorithm for determining the division of systematic and random components based on the wafermap (Sort) data. The random components are then broken down into various front-end (leakage) and backend (metal) issues. Although no validation has been made regarding the accuracy of the partition, the combined model has shown a greater than 90% correlation to reality over a high intensity ramp period of several months.
Starting Page	167
Ending Page	169
File Size	322579
Page Count	3
File Format	PDF
ISBN	0780327136
ISSN	10788743
DOI	10.1109/ASMC.1995.484361
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-11-13
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling Yield estimation Semiconductor device testing Fabrication Semiconductor devices Production Partitioning algorithms Degradation Failure analysis Displays
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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