NDLI: Wafer bonding using fluxless process with Sn-rich Sn-Au dual-layer structure

Content Provider	IEEE Xplore Digital Library
Author	Lee, C.C. Jongsung Kim
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., California Univ., Irvine, CA, USA (Lee, C.C.; Jongsung Kim)
Abstract	In many devices and packaging applications, it has been an engineering dream to be able to bond two entire wafers of the same material or of different materials with a thin metallic joint. Many new device concepts cannot be implemented because of the lack of this technology. An obvious idea to achieve this is to use solders. However, the need of using flux in the soldering process prohibits achieving void-free and uniform solder joint because flux and flux residues can be easily trapped in the joint, resulting in voids and uneven solder layer. Thus, it seems that a solution to this is to develop a soldering process that does not require the use of flux, i.e, fluxless or flux-free. In this paper, we report our initial success of bonding two 2-inch silicon wafers using Sn-rich Sn-Au dual-layer structure that is produced by electroplating process. No flux is used in the bonding process. It is much harder to achieve fluxless characteristic using Sn-rich Sn-Au alloys than Sn20Au80 eutectic alloy. The resulting Sn-rich solder joint layer, about 10 /spl mu/m in thickness, is very uniform over the entire 2-inch sample. In the initial run, two samples are produced. The quality of the joint is examined using reflection-mode scanning acoustic microscope (SAM) and X-ray micro-imaging technique. Results of these two methods indicate that the joints are of high quality. Of these two samples, the better one shows nearly perfect joint with only 2% of possible void area. More studies and evaluation are needed to further extend this method to larger wafers and to wafer materials other than silicon. This initial success shows that it is indeed possible to bond entire wafers together with a thin metallic joint of high quality.
Starting Page	105
Ending Page	109
File Size	3515640
Page Count	5
File Format	PDF
ISBN	0780390857
ISSN	15505723
e-ISBN	0780390865
DOI	10.1109/ISAPM.2005.1432057
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-03-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wafer bonding Gold Soldering Tin Temperature Packaging Silicon Inorganic materials Joining materials Optical devices
Content Type	Text
Resource Type	Article

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