NDLI: Flip Chip molding - Recent progress in flip chip encapsulation

Content Provider	IEEE Xplore Digital Library
Author	Braun, T. Becker, K.-F. Koch, M. Bader, V. Aschenbrenner, R. Reichl, H.
Copyright Year	2002
Description	Author affiliation: Fraunhofer Inst. for Reliability & Microintegration, Berlin, Germany (Braun, T.)
Abstract	As the development of microelectronics is still driving towards further miniaturization, Flip Chip technology has been widely accepted as a means for. maximum miniaturization with additional advantages. These are shortest interconnect length for minimum signal disturbance and simultaneous interconnection leading to reduced process times especially for high I/O counts and for RF applications. Flip Chip technology allows for reliabilities required for automotive applications, but to achieve this goal, a plastic encapsulant, the so called underfiller, has to be used. Conventionally a liquid epoxy resin is dispensed near the Flip Chip and is driven by capillary action under the chip. New material developments for transfer molding allow now underfilling and overmolding in one single transfer molding step. Existing standard equipment for encapsulation can be used and no additional process step for underfill dispensing is required. Molded Flip Chips have the potential of high reliability as the low CTE of the flip chip molding compound reduces the thermal mismatch. State of the art in FC molding is the encapsulation of Single Chip Packages as BGA or CSP. Trends of the market driving at SIPs with an integration of different devices as e.g. SMD and FC. Therefore the high reliable encapsulation of these hybrid packages with inhomogeneous topography is the future goal. For the qualification of Flip Chip Molding a test vehicle has been designed at Fraunhofer IZM. This test vehicle for process evaluation allows the encapsulation and underfilling of a single flip chip. Process development is described with a focus on Flip Chip and SIP molding challenges. Here the encapsulation process demands are filling of extremely small gaps without air entrapments, undisturbed bond integrity while molding at temperatures near melting point of the solder and increased pressures and venting of the mold. Device reliability demands are reduced warpage and optimum adhesion of the molding compound to solder mask, solder and die, even in harsh environment. Different materials available on the market are evaluated regarding process behavior and principal applicability for Flip Chip encapsulation. Nondestructive and destructive analysis is used to determine the failures occurring as voids and delaminations in initial state and during reliability investigations. In summary a status of the Flip Chip Molding technology is given.
Sponsorship	IEEE Components, Packaging & Manuf. Technol. (CPMT) Packaging Res. Centr at Georgia Tech (USA)
Starting Page	151
Ending Page	159
File Size	1168662
Page Count	9
File Format	PDF
ISBN	0780374347
DOI	10.1109/ISAPM.2002.990379
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-03-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip chip Encapsulation Transfer molding Packaging Testing Vehicles Microelectronics RF signals Signal processing Lead
Content Type	Text
Resource Type	Article

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