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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Manjula, S. Sundararaman, V. Sitaraman, S.K. Wong, C.P. Wu, J. Pike, R.T. |
| Copyright Year | 1999 |
| Description | Author affiliation: George W. Woodruff Sch. of Mech. Eng., Georgia Inst. of Technol., Atlanta, GA, USA (Manjula, S.) |
| Abstract | The fabrication of high-density interconnect structures typically involves sequential processing of alternate layers of thin organic dielectric materials and conducting copper lines. With the continued push toward low-cost fabrication, large-area processing of thin-film materials is being aggressively pursued by the electronic packaging industry. The objective of the ongoing work at Georgia Tech in collaboration with the MCM-D consortium is to develop innovative materials, models, and processing techniques to facilitate large-area processing of alumina and silicon tiles. As the alumina and silicon tiles are commercially available in smaller dimensions, a palletization approach has been developed to facilitate large-area processing. In the palletization approach, alumina and silicon tiles are attached to re-usable glass pallets with an in-house developed thermally-stable, reworkable, and highly-compliant adhesive. |
| Starting Page | 48 |
| Ending Page | 52 |
| File Size | 503016 |
| Page Count | 5 |
| File Format | |
| ISBN | 0930815564 |
| DOI | 10.1109/ISAPM.1999.757285 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1999-03-14 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Dielectric materials Silicon Tiles Fabrication Conducting materials Copper Dielectric thin films Electronics packaging Electronics industry Textile industry |
| Content Type | Text |
| Resource Type | Article |
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