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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Park, S.-M. Alexander, W.E. Kim, J.H. Batchelor, W.E. Krakow, W.T. |
| Copyright Year | 1988 |
| Description | Author affiliation: Dept. of Electron. Comput. Eng., North Caroline State Univ., Raleigh, NC, USA (Park, S.-M.; Alexander, W.E.) |
| Abstract | The authors present a high-performance VLSI architecture for two-dimensional (2-D) digital signal processing applications. The architecture uses a specially designed digital signal processor (DSP) as a node in a multiprocessor system for real-time or near-real-time 2-D signal processing. The DSP is custom-designed and has a throughput of two multiplications and three additions in a single cycle. It has wavefront-array-processor properties and operates asynchronously in a multiprocessor system. This architecture extends the concept of using a single processor to the use of a multiprocessor system.< |
| Starting Page | 582 |
| Ending Page | 585 |
| File Size | 300123 |
| Page Count | 4 |
| File Format | |
| ISBN | 0818608722 |
| DOI | 10.1109/ICCD.1988.25767 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1988-10-03 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Very large scale integration Real time systems Signal processing Signal processing algorithms Digital signal processing chips Difference equations Digital signal processing Multiprocessing systems Computer architecture Finite difference methods |
| Content Type | Text |
| Resource Type | Article |
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