NDLI: Variable reduction in MOS timing models

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Variable reduction in MOS timing models

Content Provider	IEEE Xplore Digital Library
Author	Zukowski, C. Chen, D.-P.
Copyright Year	1988
Description	Author affiliation: Columbia Univ., New York, NY, USA (Zukowski, C.)
Abstract	It is shown how careful parameter reduction can be used to produce simple but very accurate macromodels for complex logic circuits. To model input and output voltage waveforms, the authors use approximations that are time-scaled and time-shifted versions of 'typical' waveforms rather than highly simplified waveforms such as ramps. To model devices, they use scaled nonlinear characteristics. Furthermore, it is shown that the technique of scaling and shifting time to obtain the response of a large class of circuits from that of a single test case applies to very complex circuit models, and can be used to handle two input parameters in a very simplified manner. Finally, to illustrate the reduced-parameter macromodeling process, the authors test a simple table-lookup CMOS delay estimation algorithm.<>
Starting Page	124
Ending Page	128
File Size	331808
Page Count	5
File Format	PDF
ISBN	0818608722
DOI	10.1109/ICCD.1988.25675
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1988-10-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Circuit testing CMOS logic circuits Semiconductor device modeling Logic circuits Voltage Logic testing CMOS process Delay estimation Logic devices
Content Type	Text
Resource Type	Article

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