NDLI: Formal semantics of VHDL for verification of circuit designs

Content Provider	IEEE Xplore Digital Library
Author	Hua, G.X. Zhang, H.
Copyright Year	1993
Description	Author affiliation: Dept. of Comput. Sci., Iowa Univ., IA, USA (Hua, G.X.; Zhang, H.)
Abstract	Despite of the recent progress on formal verification of circuit designs, there exists a big gap between the hardware designers and the people who conduct formal verification (called verifiers), because of the lack of common specification languages. To solve this problem, we choose VHDL, a standard hardware design language, and enrich it properly so that the designer and the verifier has a unified platform to design and verify circuits. We develop a denotational semantics for (a significant subset of) VHDL, and based on this semantics we implement a prototype translator which automatically translates VHDL into logic formulas. We have used this translator and a theorem prover for formally verifying both combinatorial and sequential (synchronous) circuits written in VHDL.<>
Starting Page	446
Ending Page	449
File Size	376406
Page Count	4
File Format	PDF
ISBN	0818642300
DOI	10.1109/ICCD.1993.393336
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-10-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Formal verification Circuit synthesis Specification languages Hardware design languages Logic circuits Microprocessors Logic design Computer science Prototypes Automatic logic units
Content Type	Text
Resource Type	Article

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