NDLI: Pseudoexhaustive BIST for sequential circuits

Content Provider	IEEE Xplore Digital Library
Author	Kagaris, D. Tragoudas, S. Bhatia, D.
Copyright Year	1993
Description	Author affiliation: Comput. Sci. Program, Dartmouth Coll., Hanover, NH, USA (Kagaris, D.)
Abstract	We present a method that can be used to test a sequential circuit pseudoexhaustively or almost pseudoexhaustively using LFSR/SRs as ATPGs with d-2/sup w/ test patterns, where d is the sequential depth and w is the input dependency limit. Our approach is based on the following techniques: (1) Use of LFSR/SRs as ATPGs (2) Rearrangement of the flip-flops of the circuit by retiming so that the hardware overhead for breaking all cycles and bounding the sequential depth is minimized. (3) Introduction of bypass storage cells (BSCs) so that no combinational element in the circuit has input dependence greater than a user-defined constant w. (4) Introduction of bypass delay cells (BDCs) so that the graph becomes more easily balanced or approximately balanced. Comparative experimental results indicate that our method behaves better than full-scan. It also outperforms a previous approach which, not only does not provide for on-chip TPG, but also requires O(q-f-2/sup 2/) test patterns, where q is the total number of primary or pseudoprimary outputs in the circuit and f is the total number of flip-flops.<>
Starting Page	523
Ending Page	527
File Size	654269
Page Count	5
File Format	PDF
ISBN	0818642300
DOI	10.1109/ICCD.1993.393322
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-10-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Sequential circuits Circuit testing Flip-flops Sequential analysis Combinational circuits Computer science Hardware Educational institutions Delay
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Retiming for BIST-sequential circuits

Computer-aided design of pseudoexhaustive BIST for semiregular circuits

Synthesis and retiming for the pseudo-exhaustive BIST of synchronous sequential circuits

Exploiting ghost-FSMs as a BIST structure for sequential machines

Enhanced technique for built-in self-test of sequential logic

Partial set for flip-flops based on state requirement for non-scan BIST scheme

Test-per-clock testing of the circuits with scan

On minimizing hardware overhead for pseudoexhaustive circuit testability

An improved cellular automata-based BIST architecture for sequential circuits

Pseudoexhaustive BIST for sequential circuits

Similar Documents

Retiming for BIST-sequential circuits

Computer-aided design of pseudoexhaustive BIST for semiregular circuits

Synthesis and retiming for the pseudo-exhaustive BIST of synchronous sequential circuits

Exploiting ghost-FSMs as a BIST structure for sequential machines

Enhanced technique for built-in self-test of sequential logic

Partial set for flip-flops based on state requirement for non-scan BIST scheme

Test-per-clock testing of the circuits with scan

On minimizing hardware overhead for pseudoexhaustive circuit testability

An improved cellular automata-based BIST architecture for sequential circuits

Pseudoexhaustive BIST for sequential circuits