NDLI: Pollution control caching

Content Provider	IEEE Xplore Digital Library
Author	Walsh, S.J. Board, J.A.
Copyright Year	1995
Description	Author affiliation: IBM Corp., Research Triangle Park, NC, USA (Walsh, S.J.)
Abstract	The bandwidth mismatch of today's high speed processors and standard DRAMS is between a factor of 10 to 50. From 1995 to the year 2000 this mismatch is expected to grow to three orders of magnitude, necessitating greater emphasis for on-chip caches. Today on-chip caches typically consume from 20% to 50% of the total chip area and their cost is mostly a function of the chip area they consume. Clearly, any technique which can maintain memory performance and reduce chip area requirements is extremely important. In this paper we present two novel cache architectures called pollution control caching (PCC) and pollution control caching plus victim buffering (PCC+VB). We have used trace driven simulation to obtain miss ratio statistics and we developed analytical models of the expected clock cycles per instruction (E[CPI]) for each architecture and cache size studied. Analytical models were parameterized with the results of our trace driven simulation. These models incorporate provisions to study the effect that on-chip cache size has on access time, and the effect that this and different main memory latencies have on the E[CPI]. Chip area models were also developed for each architecture and used as a basis for comparison. Finally, we used ANOVA techniques to better quantify the differences in the miss rate performance of the cache sizes and cache architectures studied. Our research has shown that, given the constraints of our design space, PCC+VB equipped caches can match the miss rate performance and E[CPI] of direct napped caches that require greater than five times the silicon area.
Starting Page	300
Ending Page	306
File Size	648665
Page Count	7
File Format	PDF
ISBN	0818671653
ISSN	10636404
DOI	10.1109/ICCD.1995.528825
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-10-02
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pollution control Analytical models Bandwidth Random access memory Cost function Statistical analysis Clocks Delay Analysis of variance Silicon
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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