NDLI: On-the-Fly Multi-base Recoding for ECC Scalar Multiplication without Pre-computations

Content Provider	IEEE Xplore Digital Library
Author	Chabrier, T. Tisserand, A.
Copyright Year	2013
Description	Author affiliation: INRIA Centre Rennes - Bretagne Atlantique, Univ. Rennes 1, Lannion, France (Chabrier, T.) \|\| INRIA Centre Rennes - Bretagne Atlantique, Lannion, France (Tisserand, A.)
Abstract	Scalar recoding is popular to speed up ECC scalar multiplication: non-adjacent form, double-base number system, multi-base number system. But fast recoding methods require pre-computations: multiples of base point or off-line conversion. In this paper, we present a multi-base recoding method for ECC scalar multiplication based on i) a greedy algorithm starting least significant terms first, ii) cheap divisibility tests by multi-base elements and iii) fast exact divisions by multi-base elements. Multi-base terms are obtained on-the-fly using a special recoding unit which operates in parallel to curve-level operations and at very high speed. This ensures that all recoding steps are performed fast enough to schedule the next curve-level operations without interruptions. The proposed method can be fully implemented in hardware without pre-computations. We report FPGA implementation details and very good performances compared to state-of-art results.
Sponsorship	IEEE Comput. Soc.
Starting Page	219
Ending Page	228
File Size	316086
Page Count	10
File Format	PDF
ISBN	9781467356442
ISSN	10636889
DOI	10.1109/ARITH.2013.17
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Field programmable gate arrays Hardware Table lookup Cryptography Standards exact division by constant elliptic curve cryptography scalar multiplication DBNS MBNS divisibility test
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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