NDLI: MBus: An ultra-low power interconnect bus for next generation nanopower systems

Content Provider	IEEE Xplore Digital Library
Author	Pannuto, P. Yoonmyung Lee Ye-Sheng Kuo ZhiYoong Foo Kempke, B. Gyouho Kim Dreslinski, R.G. Blaauw, D. Dutta, P.
Copyright Year	2015
Description	Author affiliation: Electr. Eng. & Comput. Sci. Dept., Univ. of Michigan, Ann Arbor, MI, USA (Pannuto, P.; Yoonmyung Lee; Ye-Sheng Kuo; ZhiYoong Foo; Kempke, B.; Gyouho Kim; Dreslinski, R.G.; Blaauw, D.; Dutta, P.)
Abstract	As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 $mm^{3}$ MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus 's feature set.
Starting Page	629
Ending Page	641
File Size	2938488
Page Count	13
File Format	PDF
e-ISBN	9781509002566
DOI	10.1145/2749469.2750376
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-06-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Low-power electronics Resistors Clocks Chirp Tuning Circuit faults Wires
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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