NDLI: High Level Fixed Point VLSI Design with Automated Clock Gating

Content Provider	IEEE Xplore Digital Library
Author	Agarwal, N. Dimopoulos, N.
Copyright Year	2007
Description	Author affiliation: Victoria Univ., Victoria (Agarwal, N.; Dimopoulos, N.)
Abstract	Here we present a high level VLSI design platform, which supports the use of fixed point operations and automated clock gating of registers. This platform has been implemented by extending the CoDeL design suite. CoDeL allows hardware description at the algorithm level, and thus dramatically reduces design time. Also, it automatically inserts clock gating at the behavioral level to reduce dynamic power dissipation in the resulting architecture. This is, to our knowledge, the first hardware design environment that allows an algorithmic description of a component and yet produces a power aware design. We use the DSPstone benchmark to thoroughly evaluate this fixed point design platform for the design of power efficient DSP architectures. We find that, compared to a modern DSP, the CoDeL platform produces designs with somewhat slower run times but dramatically lower power dissipation. Next we use power analysis to compare the effectiveness of CoDeL's automated clock gating as compared to automated clock gating using synopsys tools. A simulation based power analysis shows that CoDeL's clock gating provides 16% more power savings than Synopsys' automated clock gating alone.
Starting Page	359
Ending Page	362
File Size	154187
Page Count	4
File Format	PDF
ISBN	9781424411894
DOI	10.1109/PACRIM.2007.4313248
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-22
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Clocks Power dissipation Digital signal processing Hardware Algorithm design and analysis Libraries Circuit testing Kernel Benchmark testing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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