NDLI: Input- and Output-Based Shared-Memory Crosspoint-Buffered Packet Switches for Multicast Traffic Switching and Replication

Content Provider	IEEE Xplore Digital Library
Author	Ziqian Dong Rojas-Cessa, R.
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ (Ziqian Dong; Rojas-Cessa, R.)
Abstract	The incorporation of broadcast and multimedia- on-demand services are expected to increase multicast traffic in packet networks, and therefore in switches and routers. Combined input-crosspoint buffered (CICB) switches can provide high performance under uniform multicast traffic, however, at the expense of $N^{2}$ crosspoint buffers. In this paper, we introduce an output-based shared-memory crosspoint-buffered (O-SMCB) packet switch where the crosspoint buffers are shared by two outputs and use no speedup. The proposed switch provides high performance under admissible uniform and nonuniform multicast traffic models while using 50% of the memory used in CICB switches. Furthermore, the O-SMCB switch provides higher throughput than an SMCB switch with buffers shared by inputs, or I-SMCB, previously proposed, despite the strong similarities between the architectures of these two switches. In this paper, we study the performance of the O-SMCB switch under uniform and nonuniform multicast traffic models and compare it to the I-SMCB switch.
Starting Page	5659
Ending Page	5663
File Size	144142
Page Count	5
File Format	PDF
ISBN	9781424420759
DOI	10.1109/ICC.2008.1060
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-19
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Packet switching Switches Traffic control Unicast Telecommunication traffic Throughput Fabrics Communication switching Buffer storage Communications Society
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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