NDLI: Accurate models for estimating area and power of FPGA implementations

Content Provider	IEEE Xplore Digital Library
Author	Lanping Deng Sobti, K. Chakrabarti, C.
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ (Lanping Deng; Sobti, K.; Chakrabarti, C.)
Abstract	This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficient design space exploration in an automated algorithm-architecture codesign framework. Detailed models for accurately estimating the number of slices, block RAMs and 18times18-bit multipliers for fixed point and floating-point IP cores have been developed. These models are also utilized to develop accurate power models that consider the effect of logic power, signal power, clock power and I/O power. In all cases, the model coefficients have been derived by using curve fitting or regression analysis. The modeling error for the IP cores is very small (average 0.95%). The error for fairly large examples such as floating point implementation of 8-point FFTs is also quite small; it is 1.87% for estimation of number of slices and 3.48% for estimation of power consumption.
Starting Page	1417
Ending Page	1420
File Size	207295
Page Count	4
File Format	PDF
ISBN	9781424414833
ISSN	15206149
DOI	10.1109/ICASSP.2008.4517885
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-03-31
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Mathematical model Power system modeling Algorithm design and analysis Signal processing algorithms Energy consumption Table lookup State estimation Logic Clocks regression analysis area and power models FPGA implementation IP core
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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