NDLI: Simultaneous Routing and Buffer Insertion algorithm for interconnect delay optimization in VLSI layout design

Content Provider	IEEE Xplore Digital Library
Author	Hani, M.K. Shaikh-Husin, N.
Copyright Year	2008
Description	Author affiliation: Dept. of Microelectron. & Comput. Engr., Univ. Teknol. Malaysia, Skudai, Malaysia (Hani, M.K.; Shaikh-Husin, N.)
Abstract	The design of VLSI circuits today has become very challenging indeed. The main factor affecting system performance is the interconnect delay. Many algorithms have been proposed to solve the interconnect timing optimization problem. Research has shown that techniques like buffer insertion and wire-sizing have been proven to be very effective in reducing interconnect delay. This paper describes a graph-based routing algorithm to solve the interconnect delay optimization problem in a deep submicron VLSI layout routing. The algorithm finds the optimal delay routing paths with simultaneous consideration of buffer insertions and wire-sizing, while taking into account wire or buffer obstacles. The proposed algorithm, called S-RABILA (Simultaneous Routing and Buffer Insertion with Look-Ahead), utilizes a novel look-ahead technique that significantly contributes to the computational efficiency of the proposed algorithm. In this paper, the performance of S-RABILA is presented, which shows the effectiveness of the look-ahead scheme. Experimental results also indicate that the proposed algorithm provide significant improvements over similar existing VLSI routing algorithms.
Starting Page	175
Ending Page	178
File Size	215427
Page Count	4
File Format	PDF
ISBN	9781424423699
DOI	10.1109/ICM.2008.5393527
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-14
Publisher Place	United Arab Emirates
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Design optimization Very large scale integration Algorithm design and analysis Integrated circuit interconnections System performance Timing Delay effects Wire Computational efficiency VLSI routing Buffer insertion Elmore delay interconnect optimization
Content Type	Text
Resource Type	Article

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