NDLI: Parallel error tolerance scheme based on the hill climbing nature of simulated annealing

Content Provider	IEEE Xplore Digital Library
Author	Hong, C.-E. McMillin, B.M.
Copyright Year	1992
Description	Author affiliation: Dept. of Comput. Sci., Missouri Univ., Rolla, MO, USA (Hong, C.-E.; McMillin, B.M.)
Abstract	In parallelizing simulated annealing in a multicomputer, maintaining the global state S involves explicit message traffic and is a critical performance bottleneck. One way to mitigate this bottleneck is to amortize the overhead of these state updates over as many parallel state changes as possible. Using this technique introduces errors in the calculated cost C(S) of a particular state S used by the annealing process. Analytically derived bounds are placed on this error in order to assure convergence to the correct result. The resulting parallel simulated annealing algorithm dynamically changes the frequency of global updates as a function of the annealing control parameter, i.e., temperature. Implementation results on the Intel iPSC/2 are reported.<>
Starting Page	685
Ending Page	688
File Size	291931
Page Count	4
File Format	PDF
ISBN	0780305108
DOI	10.1109/MWSCAS.1992.271230
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-08-09
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Simulated annealing Error correction Computational modeling Cost function Computer errors Solid modeling Temperature Frequency synchronization Broadcasting Computer science
Content Type	Text
Resource Type	Article

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