NDLI: Performance analysis of a hierarchical interconnection network using hypercubes

Content Provider	IEEE Xplore Digital Library
Author	Tiruveedhula, V. Bedi, J.S.
Copyright Year	1992
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Wayne State Univ., Detroit, MI, USA (Tiruveedhula, V.; Bedi, J.S.)
Abstract	Presents an analysis of a mixed class of networks which can be used for interconnection of a large number of processors in which data sharing is very high. This architecture uses both binary hypercubes and a multistage interconnection network with global memory. The shared data are initially kept in the memory modules and a single copy of the data is moved in the network depending on the reference pattern of the system. In this type of architecture, the switches of the network have cache memories and also the capability to maintain directions for indicating the location of the data. However, keeping a single copy in a large system has the advantage of having reduced network traffic and also no overhead due to coherency related activities. The network is evaluated using queuing analysis to take care of the contention in the network. The performance measures are compared with that of a non-hierarchical hypercube system.<>
Starting Page	867
Ending Page	870
File Size	326989
Page Count	4
File Format	PDF
ISBN	0780305108
DOI	10.1109/MWSCAS.1992.271187
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-08-09
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance analysis Multiprocessor interconnection networks Hypercubes Tree data structures Computer networks Data engineering Computer architecture Queueing analysis Switches Cache memory
Content Type	Text
Resource Type	Article

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