NDLI: Defect clustering and classification for semiconductor devices

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A low-power reconfigurable digital pulse-shaping filter for an UTRA-TDD mobile terminal receiver

High performance low power video compression techniques for future digital video solution

Implementation of wavelet transform for image compression applications

Implementation of 3D-DCT based video encoder/decoder system

Implementation of floating point fast discrete cosine transform

Implementation of a programmable phased logic cell [FPGA]

On the use of wavelet transforms in testing for the DNL of ADCs

A high-throughput pipelined architecture for blind adaptive equalizer with minimum latency

ASIC implementation of the discrete wavelet transform

Area efficient GF(p) architectures for GF(p/sup m/) multipliers

A BIST scheme for testing the interconnects of SRAM-based FPGAs

A BIST scheme for testing a multiple FPGA system

Comparison of new and conventional low voltage current mirrors

A low-voltage MOS cascode current mirror for all current levels

New low-voltage fully-balanced wide-band differential CMOS current amplifier

Current mirrors with limiting of linear dynamic range

Frequency and Q tuning of active-LC filters

Fully integrated bandpass filters for wireless transceivers-problems and promises

Design considerations of bandpass LC filters for RF applications

Optimized synthesis of X-band microstrip side coupled bandpass filters

An on-chip GHz undersampling delta modulator

Investigations using floating-gate circuits for flash ADCs

Fat tree encoder design for ultra-high speed flash A/D converters

A parametric DCT architecture for H.263+ mobile terminals video streaming

MAP decoder architecture: soft IP for SOC applications

A co-processor for real-time energy estimation of system-on-a-chip

SoC interconnect in deep submicron

Minimum cost complex resource FPGA partition with performance refining

Block placement using the segment tree data structure from computational geometry

A genetic algorithm for mixed macro and standard cell placement

A module placement algorithm based on sequence pair by introducing the concept of clustering

Switch fabric design and performance evaluation: metrics and pitfalls

ATM switch for 2.488 Gbit/s CATV network on FPGA with a high-throughput buffering architecture

A simple synchronization method using Gold code for M-ary/DS powerline communications

Intelligent flight control: what are the flight programs and why develop this technology?

On board flight computers for flight testing small uninhabited aerial vehicles

Fighter aircraft at high angles of attack

Identification of aircraft dynamics using a SOM and local linear models

Limits on echo return loss enhancement on a voice coded speech signal

Wavelet singularity detection for image processing

A closed form frequency estimator for a noisy sinusoid

Least mean square algorithm for unbiased impulse response estimation

Some steps towards a unified motion estimation procedure

Region of interest coding for image compression

A new method for JPEG2000 region-of-interest image coding: most significant bitplanes shift

An optimized hybrid vector quantization for efficient source encoding

Data quality and grounding considerations for a medical facility

Advances in gas turbine low Btu combustion that enable integration of power and process markets

Experimental investigation of distribution transformer aged solid insulation

Reduction in hardware by allowing adder sharing in filter coefficients

ARCTAN Differentiated digital demodulator for FM/FSK digital receivers

Restrained neighborhood analog median filters

Analysis and enhancements for EBCOT in high-speed JPEG2000 architectures

Improved numerically-controlled digital sinusoidal oscillator

Fast prototyping of a DSP core

Echo cancellation in IP networks

Hardware efficient narrow band FIR filter

Design methodology for broadband delta-sigma analog-to-digital converters

Multiple description image coding using pixel interleaving and wavelet transform

A recursive approach to the design of linear-phase half-band digital filters having very sharp transition bands

A new wide dynamic range fixed point ADC for FPAs

A Universal Micro-Sensor Interface chip with network communication bus and highly programmable sensor readout

A mixed-signal IC for multiple cortical stimulation strategies

On the feasibility of cascaded single-stage distributed amplifier topology in digital CMOS technology

Dual-band switchable low noise amplifier for 5-GHz wireless LAN radio receivers

A new rf CMOS mixer with a high performance in 0.18u technology

A novel CMOS front-end circuit with low power, low noise and variable gain for 5-GHz WLAN applications

A novel approach to I/sub DDQ/ testing of mixed-signal integrated circuits

A histogram based AM-BIST algorithm for ADC characterization using imprecise stimulus

A blind identification algorithm for digital calibration of pipelined ADC

On-chip iDD pulse response method using a high-speed dynamic current sensor

Adiabatic circuits for low power logic

Ultra low power 1-bit adder cells

Energy-aware multiplier design in multi-rail encoding logic

A low-power 2.1 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic

Control versus compute power within a LEDR-style self-timed multiplier with bypass path

Utilizing BDDs for disjoint SOP minimization

Information measures in detecting and recognizing symmetries

Technology-independent delay optimization of complex CMOS circuitries

Burst erasure correction to improve the efficiency of broadband CSMA/CD

Dual stage hybrid restoration protocol for optical networks

Impact of self-similarity on performance evaluation in differential service networks

Simulation of FNBDT over Internet and 3G wireless networks

On-line gyro-based, mass-property identification for thruster-controlled spacecraft using recursive least squares

A radial basis function implementation of the adaptive dynamic programming algorithm

A reconfigurable architecture suitable for adaptive multi-resolution processing

Unsupervised self-organizing adaptive fuzzy controller (USOAFC)

A 5 MHz silicon CMOS hierarchical boost DC-DC converter design using macromodels for a 1U process

Design of COR /spl Sigma/-/spl Delta/ A/D converters amenable to capacitor scaling in switched-capacitor hardware implementations

An overview of circuits and devices research on SOI technology for analog/mixed-signal systems

CMOS current mode interpolating flash analog to digital converter

Deep Space 1 mission and observation of comet Borrelly

A study of supervised, semi-supervised and unsupervised multiscale Bayesian image segmentation

Normal mammogram classification based on regional analysis

Automatic assessment of fabric smoothness

Introduction of power electronics to electric machines lab

Performance of a fault diagnosis method based on wavelet characterization

Advanced analysis of Haar transform-based control for dc motors

High frequency model of printed-circuit-board based three-winding transformers

Tracking drifting interferences using simple cascaded second order FIR filters

Narrow-band interference rejection in DS CDMA communications using an adaptive IIR notch filter

Transforms for continuous time system modeling

Adaptive time delay estimation with noise suppression for sinusoidal signals

Nonlinear reconstruction of over-sampled coarsely quantized signals

Blind source recovery using an adaptive generalized Gaussian score function

State space blind source recovery of non-minimum phase environments

Delay and Doppler estimation using cyclostationarity based cross correlation in a multipath environment

Signal integrity improvement in the TMDS link at UXGA

Design of an analog ranking system using optical intensity comparison smart-pixels with programmable intensity offset levels

A wide dynamic range CMOS digital pixel sensor

A color image sensor using adaptive color pixels

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A merged gain-variable RF front-end design for a 2GHz WCDMA DCR application I

A 1V CMOS power amplifier for Bluetooth applications

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The C-testability analysis of the superblock carry-lookahead adder (SBCLA)

Comparison and analysis of delay elements

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Comparative study of the FireWire/spl trade/ IEEE-1394 protocol with the Universal Serial Bus and Ethernet

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Defect clustering and classification for semiconductor devices

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Unified energy conversion, power systems and power electronics lab

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The Future NarrowBand Digital Terminal

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Virtual laboratory education for persons with vision disabilities

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Realization of (g/sub m/-C) current mode filters from associated (g/sub m/-C) voltage mode filters

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SOI implementation of novel triangular layout structures for microwave power transistor applications

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ALU design using reconfigurable CMOS logic

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A novel asynchronous pipeline architecture for CISC type embedded controller, A8051

Volume 1 - 2002

Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257)

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)

42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356)

1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268)

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg

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38th Midwest Symposium on Circuits and Systems. Proceedings

Proceedings of 1994 37th Midwest Symposium on Circuits and Systems

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Proceedings of the 33rd Midwest Symposium on Circuits and Systems

Proceedings of the 32nd Midwest Symposium on Circuits and Systems,

Defect clustering and classification for semiconductor devices

Content Provider	IEEE Xplore Digital Library
Author	Kundu, B. White Jr., K.P. Mastrangelo, C.
Copyright Year	2002
Description	Author affiliation: Dept. of Syst. & Inf. Eng., Virginia Univ., Charlottesville, VA, USA (Kundu, B.; White, K.P., Jr.; Mastrangelo, C.)
Abstract	In semiconductor manufacturing, cracks, scratches, contaminants, process variations, and errors by operators or equipment are all production problems that cause defects on wafers. It is highly desirable to find and classify defect signatures recorded in the data sets for final electrical tests and to correlate these signatures with causal data residing in the corresponding process and engineering data sets. In the first part of this paper, we explore the first of these issues-automating the identification of defect clusters on individual wafers within and across lots. Selection of the right number of clusters is achieved by incorporating the Calinsky and Harabasz (CH) index. We observe that the single-link clustering algorithm works the best in detecting the right number and shape of defect clusters. In the second part of this paper, we attempt to classify clustered defect patterns using an analytical tool, called the Hough Transformation (HT), proposed by Cunningham and MacKinnon, to identify scratch defects on semiconductor wafers. We observe that HT works well in detecting a variety of scratches, including diagonal scratches and line scratches.
Sponsorship	IEEE Circuits & Syst. Soc. School of Electr. & Comput. Eng. at Oklahoma State Univ
File Size	285398
File Format	PDF
ISBN	0780375238
DOI	10.1109/MWSCAS.2002.1186923
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-08-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor devices Testing Fabrication Manufacturing processes Semiconductor device manufacture Data engineering Clustering algorithms Systems engineering and theory Production systems Shape
Content Type	Text
Resource Type	Article

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