NDLI: Low power and high speed explicit-pulsed flip-flops

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Low power and high speed explicit-pulsed flip-flops

Content Provider	IEEE Xplore Digital Library
Author	Peiyi Zhao Darwish, T. Bayoumi, M.
Copyright Year	2002
Description	Author affiliation: Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA (Peiyi Zhao; Darwish, T.; Bayoumi, M.)
Abstract	Flip-flops play an important role in building digital CMOS designs. Their design and optimization is critical for high-performance and low power systems. In this paper, we propose high-performance and low power flip-flops based on the explicit-pulsed flip-flop (EPFF). These new flip-flops eliminate the hazardous glitches associated with the original EPFF output. The Static-EPFF (SEPFF) is developed for low-power dissipation purposes; it reduces the power dissipation by 13.9%-15.7%, and it enhances the speed by 4.86%-7.87%. For high-speed objectives, the dual path single-transistor-clocked EPFF (STC-EPFF) achieves 21% enhancement in speed over EPFF at the expense of increased power dissipation (12%).
Sponsorship	IEEE Circuits & Syst. Soc. School of Electr. & Comput. Eng. at Oklahoma State Univ
File Size	266812
File Format	PDF
ISBN	0780375238
DOI	10.1109/MWSCAS.2002.1186902
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-08-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip-flops Power dissipation Clocks CMOS technology Circuit noise Delay Noise generators Buildings Design optimization Power systems
Content Type	Text
Resource Type	Article

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