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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Min Xu Kurdahi, F.J. |
| Copyright Year | 1997 |
| Description | Author affiliation: Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA (Min Xu; Kurdahi, F.J.) |
| Abstract | The importance of effective and efficient accounting of layout effects is well-established in High-Level Synthesis (HLS), since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics. This feature is highly desirable in order to avoid unnecessary iterations through the design process. In this paper, we address the problem of layout-driven scheduling-binding as these steps have a direct relevance on the final performance of the design. By producing not only an RTL netlist but also an approximate physical topology of implementation at the chip level, we ensure that the solution will perform at the predicted metric once implemented, thus avoiding unnecessary delays in the design process. |
| Starting Page | 1134 |
| Ending Page | 1137 |
| File Size | 551101 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780336941 |
| DOI | 10.1109/MWSCAS.1997.662277 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1997-08-06 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | High level synthesis Phased arrays Process design Algorithm design and analysis Field programmable gate arrays Topology Delay Design methodology Output feedback Time factors |
| Content Type | Text |
| Resource Type | Article |
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