NDLI: Logic value assignment contribution to testability analysis

Content Provider	IEEE Xplore Digital Library
Author	Kadim, H.J. Taylor, G.E.
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. Eng., Hull Univ., UK (Kadim, H.J.; Taylor, G.E.)
Abstract	Due to the increased complexity of the devices produced, test generation has become one of the more important cost factors in VLSI production. Testability measures are one attempt to reduce the test cost. There are a number of techniques adopted for the evaluation of such testability measures. Most of these are based on controllability and observability concepts. The basic idea is to associate a quantitive measure with each node in the circuit under analysis. The approach proposed in this paper operates as follows: 1) Consider the relationship among objects and evaluate testability costs accordingly; 2) Use both static and dynamic measures. Only one pass through the circuit is required. This method is more deterministic than other techniques and allows hierarchical implementation (including high level primitives).<>
Starting Page	195
Ending Page	198
File Size	433634
Page Count	4
File Format	PDF
ISBN	078031915X
DOI	10.1109/ISCAS.1994.409230
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-05-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic testing Costs Circuit testing Circuit simulation Circuit analysis Logic devices Electronic equipment testing Production Controllability Observability
Content Type	Text
Resource Type	Article

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