NDLI: An accurate and matching-free threshold voltage extraction scheme for MOS transistors

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An accurate and matching-free threshold voltage extraction scheme for MOS transistors

Content Provider	IEEE Xplore Digital Library
Author	Chong-Gun Yu Geiger, R.L.
Copyright Year	1994
Description	Author affiliation: Dept. of Electron. Eng., Inchon Univ., South Korea (Chong-Gun Yu)
Abstract	An accurate threshold voltage extraction scheme for MOS transistors is presented. The scheme differs from alternative methods recently reported in the literature in that it does not require matched replica of the transistor under test and thus can be applied more effectively and accurately to real-time on-chip applications where threshold voltage measurements are required for many transistors with various geometries and bias conditions. The proposed scheme is accurately implemented in a matching-free way using a ratio-independent switched-capacitor subtracting amplifier and a dynamic current mirror. Nonideal effects associated with these circuits are investigated.<>
Starting Page	115
Ending Page	118
File Size	447895
Page Count	4
File Format	PDF
ISBN	078031915X
DOI	10.1109/ISCAS.1994.409211
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-05-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Threshold voltage MOSFETs Geometry Mirrors Data mining Degradation Circuit testing Equations Voltage measurement Linear regression
Content Type	Text
Resource Type	Article

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