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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Thi Hong Tran Lanante, L. Nagao, Y. Kurosaki, M. Ochi, H. |
| Copyright Year | 2012 |
| Description | Author affiliation: Dept. of Computer Science and Electronics, Kyushu Institute of Technology, 680-4 Iizuka Fukuoka JAPAN (Thi Hong Tran; Lanante, L.; Nagao, Y.; Kurosaki, M.; Ochi, H.) |
| Abstract | In this paper, we present an efficient and high throughput hardware implementation of the RC4 algorithm. The main idea of the proposed architecture is the utilization of a tri-port RAM to reduce the memory resource and to increase throughput. The proposed design requires two clock cycles for generating one byte of ciphering key and uses only a block of 256 bytes RAM. These result in 50% increment of system throughput and three times reduction of RAM resource compared to the recent architectures. The proposed implementation supports variable key length from 8 to 128 bits and achieves 80 MB/s throughput at 160 MHz operating frequency. It aims to support the WEP security in the MAC layer of 600 Mbps 4×4 MIMO wireless LAN system based on IEEE 802.11n standard. |
| Starting Page | 77 |
| Ending Page | 80 |
| File Size | 490604 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467302180 |
| ISSN | 02714302 |
| e-ISBN | 9781467302197 |
| DOI | 10.1109/ISCAS.2012.6272151 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-05-20 |
| Publisher Place | Korea (South) |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Random access memory Throughput Indexes Clocks Hardware Computer architecture Algorithm design and analysis etc RC4 algorithm RC4's hardware implement WEP WLANs security tri-port RAM |
| Content Type | Text |
| Resource Type | Article |
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