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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hu, Y.H. Chen, S.-J. |
| Copyright Year | 1989 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA (Hu, Y.H.) |
| Abstract | Gate matrix layout is formulated as a planning problem where a plane (the solution steps) is generated to achieve a goal (the gate matrix layout) that consists of interacting subgoals. Each subgoal corresponds to the placement of a gate to a slot, or to the routing of a net connecting gates. The interaction among subgoals is managed with two artificial-intelligence planning techniques: hierarchical planning and metaplanning. A distance measure is defined and used to arrange the subgoals into prioritized classes in the hierarchical planning phase. Two metaplanning policies-graceful retreat and least impact-are used to decide which subgoal is to be achieved within the same priority class and how it can be achieved. In doing so, GM Plan successfully combines gate placement and net routing of the gate matrix layout into one process and has the potential to deliver better results.< |
| Starting Page | 1867 |
| Ending Page | 1870 |
| File Size | 433531 |
| Page Count | 4 |
| File Format | |
| DOI | 10.1109/ISCAS.1989.100732 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1989-05-08 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Artificial intelligence Routing Joining processes Wire Circuits Contracts MOSFETs Problem-solving Greedy algorithms Strategic planning |
| Content Type | Text |
| Resource Type | Article |
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