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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Rana, D. Weems, C.C. |
| Copyright Year | 1989 |
| Description | Author affiliation: Massachusetts Univ., Amherst, MA, USA (Rana, D.; Weems, C.C.) |
| Abstract | The architecture of a custom VLSI parallel communications switch (PARCOS) chip is described. The PARCOS chip consists of a communication matrix of 32-b serial inputs and 32-b serial outputs and an on-chip control memory. The control memory, called the connection pattern cache (CPC), is constructed so that PARCOS can hold up to 32 of the most frequently used connection patterns between its inputs and outputs. Any of these stored patterns is incrementally modifiable, and the connection pattern of the communication matrix can be switched from one stored pattern in the CPC to another, with a single instruction. This chip is used in building an easily reconfigurable, circuit-switched connection network for the interprocessor communication of the intermediate-level processors of the Image Understanding Architecture (IUA) prototype.< |
| Starting Page | 126 |
| Ending Page | 129 |
| File Size | 340710 |
| Page Count | 4 |
| File Format | |
| DOI | 10.1109/ISCAS.1989.100307 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1989-05-08 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Communication switching Switches Computer architecture Communication system control Integrated circuit interconnections Topology Signal processing algorithms Computer vision Parallel architectures Machine vision |
| Content Type | Text |
| Resource Type | Article |
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