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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jullien, G.A. Miller, W.C. |
| Copyright Year | 1989 |
| Description | Author affiliation: Windsor Univ., Ont., Canada (Jullien, G.A.; Miller, W.C.) |
| Abstract | A discussion is presented of the VLSI implementation of processing elements that can be used in very high-throughput two-dimensional signal processing systems. The architecture is based entirely on a single generic cell and forms naturally homogeneous architectures when used to implement bit-level systolic arrays over finite rings. The authors briefly discuss the cellular structure that is used to implement the bit-level arrays, introduce a novel circuit form that allows very fast processing for any CMOS technology, and, as an example, discuss the implementation of a two-dimensional computational element for high-throughput DFT processors. The VLSI array implementation for the DFT computational element is illustrated by a mask layout in a double-metal 3- mu m CMOS technology; projected throughput rates in this technology are simulated in excess of 45 M samples/s.< |
| Starting Page | 1388 |
| Ending Page | 1391 |
| File Size | 400589 |
| Page Count | 4 |
| File Format | |
| DOI | 10.1109/ISCAS.1989.100615 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1989-05-08 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Very large scale integration Digital signal processing CMOS technology Array signal processing Computer architecture Systolic arrays Circuits CMOS process Throughput Computational modeling |
| Content Type | Text |
| Resource Type | Article |
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