NDLI: Macromodeling of digital libraries for substrate noise analysis

Content Provider	IEEE Xplore Digital Library
Author	Wang, Z. Murgai, R. Roychowdhury, J.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Minnesota Univ., MN, USA (Wang, Z.)
Abstract	The demand for low cost, low power, and small area electronic device calls for system-on-a-chip (SoC) designs. Integration of complex digital blocks and high performance analog functions onto single SoCs induces signal integrity between noisy digital circuits and sensitive analog sections. Such signal integrity degrades the performance of analog circuits and even causes functional failures of victim circuits. In order to account for this interference in circuit design phases, substrate noise analysis becomes particularly important, especially in deep submicron digital and mixed-signal circuits. To this end, it is critical to estimate efficiently and accurately the noise injection from the digital circuits with tens of millions of transistors. In this work, we develop techniques that automatically extract low-complexity time-varying macromodels for digital blocks, at the cell library building phase. Tailored for substrate noise analysis, the extracted macromodel includes three major noise injection mechanisms. The efficacy and accuracy of our macromodel are confirmed in the simulation results. Thanks to the linear time-varying (LTV) model reduction based on the time-varying Pade (TVP) method, our macromodel extraction features high accuracy with affordable complexity. Equally attractive is the accurate-by-construction substrate noise model generation by merging the macromodel extraction into cell library building phase.
Sponsorship	IEEE Circuits and Syst. Soc
File Size	334138
File Format	PDF
ISBN	078038251X
DOI	10.1109/ISCAS.2004.1329701
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-05-23
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Software libraries Circuit noise System-on-a-chip Digital circuits Phase noise Costs Degradation Analog circuits Interference Circuit synthesis
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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