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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Changqi Yang Xianlong Hong Honghua Yang, H. Qiang Zhou Yici Cai Yonqiang Lu |
| Copyright Year | 2004 |
| Description | Author affiliation: Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China (Changqi Yang; Xianlong Hong) |
| Abstract | Mixed mode placement (MMP) is characterized by a number of same-height standard cells mixed with scattering big blocks in a fixed die. The variety of size and number of blocks introduces challenges to existing algorithms in achieving reasonable solution quality and running time. A new design flow named recursive mixed mode placement (RMMP) is presented in this paper to provide a solution of MMP with this circuit's variety of block configuration taken into account. It starts from recursively partitioning circuits to form a tree of virtual blocks in the different condition of the size and number of blocks as well as the logical or physical hierarchy. Then it combines floorplan on block level and quadratic place (Q-place) on cell level to complete the global placement. Our approach takes advantage of combining floorplan and Q-place algorithms to fit the variety of circuit's components. The combined approach improves the algorithm efficiency and obtains satisfactory results of MMP in terms of wire length and running time on various industry and academia test cases. |
| Sponsorship | IEEE Circuits and Syst. Soc |
| File Size | 241060 |
| File Format | |
| ISBN | 078038251X |
| DOI | 10.1109/ISCAS.2004.1329463 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-05-23 |
| Publisher Place | Canada |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hidden Markov models Law Legal factors Computer science Delay Design methodology Wire Algorithm design and analysis Circuit analysis Shape |
| Content Type | Text |
| Resource Type | Article |
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