NDLI: Quick and effective buffered legitimate skew clock routing

Content Provider	IEEE Xplore Digital Library
Author	Meng Zhao Xinjie Wei Yici Cai Xianlong Hong
Copyright Year	2004
Description	Author affiliation: Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China (Meng Zhao; Xinjie Wei; Yici Cai; Xianlong Hong)
Abstract	We propose a new quick and effective buffered legitimate skew clock routing algorithm BLST. We analyze the optimal buffer position in the clock path, and conclude the sufficient and heuristic condition for buffer insertion in clock net. During the routing process, this algorithm integrates topology generation, buffer insertion, and node merge together, and performs them parallel. Compared with the method of X. Zheng et al. (1999) of buffer insertion after skew clock routing, BLST improves the maximal clock delay by at least 22%. Compared with legitimate skew clock routing algorithm of M. Zhao et al. (2003) with no buffer, this algorithm further decreases the total wire length and gets from 42% to 82% reduction on the maximal clock delay. The experimental results show our algorithm is quick and effective.
Sponsorship	IEEE Circuits and Syst. Soc
File Size	246674
File Format	PDF
ISBN	078038251X
DOI	10.1109/ISCAS.2004.1329531
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-05-23
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Routing Delay Wire Topology Very large scale integration Scheduling Algorithm design and analysis Capacitance Computer science
Content Type	Text
Resource Type	Article

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