NDLI: Shift-accumulator ALU centric JPEG2000 5/3 lifting based discrete wavelet transform architecture

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Volume 5 - 2003

A micropower envelope detector for audio applications [hearing aid applications]

A smart bi-directional telemetry unit for retinal prosthetic device

Design of an integrated potentiostat circuit for CMOS bio sensor chips

Distributed neurochemical sensing: in vitro experiments

Visual signal processing and image understanding in biomedical systems

An efficient blood vessel detection algorithm for retinal images using local entropy thresholding

Phase analysis of DNA genomic signals

Enhanced time-frequency features for neonatal EEG seizure detection

An optimal feature set for seizure detection systems for newborn EEG signals

An ultra low-power dynamic translinear cardiac sense amplifier for pacemakers

A micropower analog VLSI processing channel for bionic ears and speech-recognition front ends

A high-rate frequency shift keying demodulator chip for wireless biomedical implants

A very low-power 8-bit /spl Sigma//spl Delta/ converter in a 0.8 /spl mu/m CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8 V

A cortical stimulator with monitoring capabilities using a novel 1 Mbps ASK data link

VLSI implementation of wireless bi-directional communication circuits for micro-stimulator

A CMOS micro-power wideband data/power transfer system for biomedical implants

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xLIW - a scaleable long instruction word [DSP applications]

Field programmable gate arrays and analog implementation of BRIN for optimization problems

A low-complexity power-efficient signaling scheme for chip-to-chip communication

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Signaling capacity of FR4 PCB traces for chip-to-chip communication

A CMOS charge pump for sub-2.0 V operation

New dynamic logic-level converters for high performance application

Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit

Area-efficient memory-based architecture for FFT processing

Optimization of power consumption for an ARM7-based multimedia handheld device

Loop scheduling for minimizing schedule length and switching activities

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5 GHz pipelined multiplier and MAC in 0.18 /spl mu/m complementary static CMOS

A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder

Low cost logarithmic techniques for high-precision computations

A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems

A flexible LUT-based carry chain for FPGAs

Low-error fixed-width squarer design

Area-time optimal adder with relative placement generator

About the performances of the Advanced Encryption Standard in embedded systems with cache memory

An efficient inverse multiplier/divider architecture for cryptography systems

On the hardware implementations of the SHA-2 (256, 384, 512) hash functions

A fast-serial finite field multiplier without increasing the number of registers

Shift-accumulator ALU centric JPEG2000 5/3 lifting based discrete wavelet transform architecture

Design of a self-timed asynchronous parallel FIR filter using CSCD

Accurate delay model and experimental verification for current/voltage mode on-chip interconnects

Area-effective FIR filter design for multiplier-less implementation

An approach for improving the speed of content addressable memories

Watermarking based IP core protection

History-based memory mode prediction for improving memory performance

A coding method for 123 decision diagram pass transistor logic circuit synthesis

Novel recharge semi-floating-gate CMOS logic for multiple-valued systems

An efficient transistor optimizer for custom circuits

A framework of evolutionary graph generation system and its application to circuit synthesis

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A fast algorithm to reduce 2-dimensional assignment problems to 1-dimensional assignment problems for FPGA-based fault simulation

Design of a switch for network on chip applications

Modulo (2/sup p/ /spl plusmn/ 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic

A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders

High-radix redundant circuits for RNS modulo r/sup n/ - 1, r/sup n/, or r/sup n/ + 1

Area efficient, high speed parallel counter circuits using charge recycling threshold logic

Virtual-scan: a novel approach for software-based self-testing of microprocessors

Design of programmable embedded IF source for design self-test

Formal verification of LTL formulas for SystemC designs

Open computation tree logic with fairness

Design and experimental results of a CMOS flip-flop featuring embedded threshold logic

Variable sampling window flip-flop for low-power application

Design of MUX, XOR and D-latch SCL gates

Parameterized and low power DSP core for embedded systems

Macromodel for short circuit power dissipation of submicron CMOS inverters and its application to design CMOS buffers

Inductive interconnect width optimization for low power

On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms

Low operating voltage and short settling time CMOS charge pump for MEMS applications

Analysis of output ripple in multi-phase clocked charge pumps

No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications

A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining

Minimizing switching activity in input word by offset and its low power applications for FIR filters

A low-complexity correlation algorithm

A low-power CMOS integrated circuit for bearing estimation

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A novel hybrid pass logic with static CMOS output drive full-adder cell

Ultra low voltage, low power 4-2 compressor for high speed multiplications

Design of a 32-bit squarer - exploiting addition redundancy

Area and power optimization of FPRM function based circuits

A configurable divider using digit recurrence

A low power asynchronous GF(2/sup 173/) ALU for elliptic curve crypto-processor

Low power block based FIR filtering cores

Dynamic operand transformation for low-power multiplier-accumulator design

Voltage scaling and repeater insertion for high-throughput low-power interconnects

A triple port RAM based low power commutator architecture for a pipelined FFT processor

DSP engine for ultra-low-power audio applications [codec application]

An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication

A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers

An active leakage-injection scheme applied to low-voltage SRAMs

Low-power and low-voltage fully parallel content-addressable memory

A low power charge sharing ROM using dummy bit lines

A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter

Increasing the locality of memory access patterns by low-overhead hardware address relocation

A semi-Gray encoding algorithm for low-power state assignment

A power efficient register file architecture using master latch sharing

A new synchronous mirror delay with an auto-skew-generation circuit

An SOI 4 transistors self-refresh ultra-low-voltage memory cell

High performance and low power completion detection circuit

Low-power CMOS circuit techniques for motion estimators

Power-delay tradeoffs in residue number system

Upper and lower bounds on FSM switching activity

Exploiting reconfigurability for low-power control of embedded processors

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MTCMOS with outer feedback (MTOF) flip-flops

Comparison of synthesized bus and crossbar interconnection architectures

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Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI

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Clock recovery in high-speed multilevel serial links

Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity

Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning

Plic-Plac: a novel constructive algorithm for placement

Graph-based approach to evaluate net routability of a floorplan

CSD multipliers for FPGA DSP applications

Electrical characteristics of multi-layer power distribution grids

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Noise-constrained interconnect optimization for nanometer technologies

A crosstalk aware two-pin net router

Placement with symmetry constraints for analog layout using red-black trees

Arbitrary convex and concave rectilinear block packing based on corner block list

General iterative heuristics for VLSI multiobjective partitioning

Tile-graph-based power planning

High performance asynchronous bus for SoC

Minimizing coupling jitter by buffer resizing for coupled clock networks

Statistical modeling of gate-delay variation with consideration of intra-gate variability

Efficient core designs based on parameterized macrocells with accurate delay models

Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST]

A resource balancing approach to SoC test scheduling

Aliasing probability calculations in nonlinear compactors

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Experimental evaluation and validation of a BIST algorithm for characterization of A/D converter performance

Systematic test program generation for SoC testing using embedded processor

On efficient extraction of partially specified test sets for synchronous sequential circuits

Combinational circuit fault diagnosis using logic emulation

The fault detection of cross-check test scheme for infrared FPA

Measurement and SPICE prediction of sub-picosecond clock jitter in A/D converters

A tester-on-chip implementation in 0.18/spl mu/ CMOS utilizing a MEMS interface

On-chip debug support for embedded Systems-on-Chip

A modular test structure for CMOS mismatch characterization

Efficient BIST schemes for RNS datapaths

BIST for clock jitter measurements

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Case study of cost and performance trade-off analysis for mixed-signal integration in system-on-chip

Fast prototyping of reconfigurable architectures from a C program

Interface design approach for system on chip based on configuration

Circuit design from optimal wavelet packet series expressions

An Integrated Framework of Design Optimization and Space Minimization for DSP applications

Reducing the number of variable movements in exact BDD minimization

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Control signal sharing of asynchronous circuits using datapath delay information

Multitasking in hardware-software codesign for reconfigurable computer

System-on-Chip design using intellectual properties with imprecise design costs

An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications

A systolic multiplier with LSB first algorithm over GF(2/sup m/) which is as efficient as the one with MSB first algorithm

A logic-aware layout methodology to enhance the noise immunity of domino circuits

Partial rerouting algorithm for reconfigurable VLSI arrays

Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism

A fault tolerant hardware based file system manager for solid state mass memory

Mixed-signal VLSI implementation of the Products of Experts' contrastive divergence learning scheme

Analog continuous-time recurrent decision circuit with high signal-voltage symmetry and delay-time equality

Hybrid neural network architecture for age identification of ancient Kannada scripts

Plastic NNs for biochemical detection

Algorithms for computating principal and minor invariant subspaces of large matrices

Analysis of global exponential stability for a class of bidirectional associative memory networks

Synthesis for symmetric weight matrices of neural networks

Exponential periodicity of neural networks with delays

A highly scalable 3D chip for binary neural network classification applications

Compact image compression using simplicial and ART neural systems with mixed signal implementations

RBF network based on genetic algorithm optimization for nonlinear time series prediction

Neurosearch: a program library for neural network driven search meta-heuristics [VLSI netlist partitioning example]

Artificial neural networks as rain attenuation predictors in earth-space paths

Stepsize control in NLMS acoustic echo cancellation using a neural network

Development of a decision support system for heart disease diagnosis using multilayer perceptron

Preprocessing based solution for the vanishing gradient problem in recurrent neural networks

Medical data mining model for oriental medicine via BYY Binary Independent Factor Analysis

Global asymptotic stability of a larger class of delayed neural networks

Global optimization of neural network weights using subenergy tunneling function and ripple search

A recurrent neural network for 1-D phase retrieval

Class-based neural network method for fault location of large-scale analogue circuits

Dynamical hysteresis neural networks for graph coloring problem

Application of critical support vector machine to time series prediction

A neural network to retrieve atmospheric parameters from infrared high resolution sensor spectra

A convolutional neural architecture: an application for defects detection in continuous manufacturing systems

New criteria for the existence of stable equilibrium points in nonsymmetric cellular neural networks

An area-efficient full-wave current rectifier for analog array processing

CMOS implementation of an extended CNN cell to deal with complex dynamics

On dynamic behavior of full range CNNs

High speed road boundary detection on the images for autonomous vehicle with the multi-layer CNN

Cellular neural networks with second-order cells and their pattern forming properties

A new method for implementing gate operations in a quantum factoring algorithm

Periodic orbits and bifurcations in one-dimensional arrays of Chua's circuits

Fuzzy power control with weighting function in DS-CDMA cellular mobile communication system

Fuzzy temporal representation and reasoning [hot-cold water mixer simulator example]

Synchronization in arrays of fuzzy chaotic oscillators

A high speed scalable and reconfigurable fuzzy controller

Design of a Self-Organizing Learning Array system

Fuzzy Associative Database for multiple planar object recognition

Tight bounded localization of facial features with color and rotational independence

Analog CMOS implementation of Gallager's iterative decoding algorithm applied to a block turbo code

Learning temporal correlations in biologically-inspired aVLSI

Pulse mode neuron with leakage integrator and additive random noise

Lossless non-arbitrated address-event coding

A wide-field direction-selective aVLSI spiking neuron

Focal plane image segmentation using locally interconnected spiking pixel architecture

Design of a reduced KII set and network in analog VLSI

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The IEEE International Symposium on Circuits and Systems, 2003. Tutorial Guide: ISCAS 2003.

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1988., IEEE International Symposium on Circuits and Systems

Shift-accumulator ALU centric JPEG2000 5/3 lifting based discrete wavelet transform architecture

Content Provider	IEEE Xplore Digital Library
Author	Tan, K.-C.B. Arslan, T.
Copyright Year	2003
Description	Author affiliation: Inst. of Micro & Nano Syst., Edinburgh Univ., UK (Tan, K.-C.B.; Arslan, T.)
Abstract	This paper presents a novel (low arithmetic unit count) hardware architecture for performing lifting-based JPEG2000's 5/3 Discrete Wavelet Transform (DWT). The architecture is built around parallel Shift-Accumulator Arithmetic Logic Units (ALUs) which can encode (with implicit embedded extension) up to five levels of transformation. The proposed architecture, which consists of three adders, two subtractor-adders and five shifters, has a significantly lower hardware count compared to the architectures proposed by K. Andra et. al. (2002) and C-J. Lian et. al. (2001). In addition, the architecture has an efficient memory organisation, which uses lesser amount of embedded memory for processing and buffering. In this paper, we present the architecture and demonstrate that it closely adheres to the JPEG2000's specification while reducing the hardware requirements and hence area and power consumption.
Sponsorship	IEEE Circuits & Syst. Soc Mahanakorn Univ. Technol
File Size	310947
File Format	PDF
ISBN	0780377613
DOI	10.1109/ISCAS.2003.1206218
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-05-25
Publisher Place	Thailand
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete wavelet transforms Hardware Computer architecture Arithmetic Energy consumption Image coding Systems engineering and theory Buildings Logic Image communication
Content Type	Text
Resource Type	Article

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