NDLI: Design of a pipelined and expandable sorting architecture with simple control scheme

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Implementation of the transposed Farrow structure

Fractional biorthogonal partners and application in signal interpolation

Multiplier-less implementation of linear phase cosine modulated filter banks with composite channel number

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Bandwidth considerations for a CALLUM transmitter architecture

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Antisymmetries in the realization of Boolean functions

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Low-power multipliers by minimizing switching activities of partial products

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A dual-band RF front-end for WCDMA and GPS applications

RF gain control in direct conversion receivers

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A high throughput context-based adaptive arithmetic codec for JPEG2000

An adaptive Viterbi algorithm based on strongly connected trellis decoding

Content-based video retrieval using motion descriptors extracted from compressed domain

Region-based relevance feedback in image retrieval

A novel video key frame extraction algorithm

A lifting based system for optimal compression and classification in the JPEG2000 framework

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A cellular nonlinear approach to decentralized locomotion control of the stick insect

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An efficient modified Phong shading algorithm & its low-complexity realization

A ring-processor based blind beamformer design for use in wireless sensor networks

A scalable sorting architecture based on maskable WTA/MAX circuit

A new pipelined adaptive DFE architecture with improved convergence rate

Design of a pipelined and expandable sorting architecture with simple control scheme

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Multirate cascaded continuous time /spl Sigma//spl Delta/ modulators

Systematic approach for discrete-time to continuous-time transformation of /spl Sigma//spl Delta/ modulators

Figure of merit based design strategy for low-power continuous-time /spl Sigma//spl Delta/ modulators

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Finite-length synthesis filters for non-uniformly time-interleaved analog-to-digital converter

A two-pass optimal motion-threading technique for 3D wavelet video coding

Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm

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Least squares solution of nearly square overdetermined sparse linear systems

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Incorporation of input glitches into power macromodeling

A coefficient memory addressing scheme for VLSI implementation of FFT processors

Random number generator architecture and VLSI implementation

The two-phase twisted-ring counter circuit

A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs

An adaptive data compression scheme for memory traffic minimization in processor-based systems

CASCADE - configurable and scalable DSP environment

Register-based reordering networks for matrix transpose

Hardware implementation of the SAFER+ encryption algorithm for the Bluetooth system

VLSI architectures for the implementation of the Wigner distribution

Architectural support for detection of sleepy eye behavior

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Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)

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Design of a pipelined and expandable sorting architecture with simple control scheme

Content Provider	IEEE Xplore Digital Library
Author	Chi-Sheng Lin Bin-Da Liu
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan (Chi-Sheng Lin; Bin-Da Liu)
Abstract	This paper presents a novel circuit for the pipelined and expandable sorting architecture that processes thirty-two 16-bit patterns at a time. This design is based on a compare-swap cell which can easily be cascaded to improve sorting performance. The sorting architecture combines suitable algorithm to sort arbitrary N data patterns. The proposed hardware architecture features layout regularity and interconnection compactness, thus it can be exploited to obtain a small and efficient hardware implementation. The whole design was fabricated by TSMC 0.35/spl mu/m SPQM CMOS process. The estimation results indicate that the sorter can work up to 66MHz with the power consumption less than 20mW under 3.3V supply voltage. This design is suitable for VLSI implementation. It can also be applied well when being embedded in digital signal processors.
Sponsorship	IEEE IEEE Circuits & Syst. Soc
File Size	243411
File Format	PDF
ISBN	0780374487
DOI	10.1109/ISCAS.2002.1010428
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sorting Hardware Signal processing algorithms Registers Integrated circuit interconnections Very large scale integration Digital signal processors Electronic mail CMOS process Energy consumption
Content Type	Text
Resource Type	Article

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