NDLI: A design of a low-power, high-accuracy, and constant-Q-tuning continuous-time bandpass filter

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A systematic technique for optimizing multiple branch FIR filters for sampling rate conversion

Implementation of the transposed Farrow structure

Fractional biorthogonal partners and application in signal interpolation

Multiplier-less implementation of linear phase cosine modulated filter banks with composite channel number

Lifting based integer wavelet transform with binary coefficients

A 50% duty-cycle correction circuit for PLL output

Bandwidth considerations for a CALLUM transmitter architecture

A 22-mW 435-MHz differential CMOS high-gain LNA for subsampling receivers

A 10-mW 435-MHz differential CMOS LNA for low-IF receivers in space applications

A monolithic low power pulsed optical encoder

A new detector architecture for optical pickup units in DVD systems

A robust edge detector for motion detection

New pixel-shared design and split-path readout of CMOS image sensor circuits

A CMOS imager with PFM/PWM based analog-to-digital converter

A differential summing amplifier for analog VLSI systems

Parameter optimization tool for enhancing on-chip network performance

Switching activity estimation of finite state machines for low power synthesis

Antisymmetries in the realization of Boolean functions

Memory exploration utilizing scheduling effects in high-level synthesis

Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions

Instruction buffering for nested loops in low power design

Evaluation on power reduction applying gated clock approaches

Low power register file architecture for application specific DSPs

Low-power multipliers by minimizing switching activities of partial products

A novel list-scheduling algorithm for the low-energy program execution

An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applications

FIR filters for compensating D/A converter frequency response distortion

Correction of transmitter gain and phase errors at the receiver

A dual-band RF front-end for WCDMA and GPS applications

RF gain control in direct conversion receivers

Design of a new signal security system

A novel adaptive algorithm applied to a class of redundant representation vector quantizers for waveform and model based coding

Spectrum management of pulse transmission by high-cut filter line

A high throughput context-based adaptive arithmetic codec for JPEG2000

An adaptive Viterbi algorithm based on strongly connected trellis decoding

Content-based video retrieval using motion descriptors extracted from compressed domain

Region-based relevance feedback in image retrieval

A novel video key frame extraction algorithm

A lifting based system for optimal compression and classification in the JPEG2000 framework

Efficient content-based CT brain image retrieval by using region shape features

A realistic mammalian retinal model implemented on complex cell CNN universal machine

A cellular nonlinear approach to decentralized locomotion control of the stick insect

Towards fast solid state DNA sequencing

Advanced neural implants using thin-film polymers

Cellular neural networks for the anticipation of epileptic seizures

A low-voltage low-noise digital buffer system

A new technique for noise-tolerant pipelined dynamic digital circuits

Novel macromodeling for on-chip RC/RLC interconnects

Optimising bandwidth over deep sub-micron interconnect

Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance

An efficient modified Phong shading algorithm & its low-complexity realization

A ring-processor based blind beamformer design for use in wireless sensor networks

A scalable sorting architecture based on maskable WTA/MAX circuit

A new pipelined adaptive DFE architecture with improved convergence rate

Design of a pipelined and expandable sorting architecture with simple control scheme

A quadrature IF mixer with high image rejection for continuous-time complex /spl Sigma//spl Delta/ modulators

Multirate cascaded continuous time /spl Sigma//spl Delta/ modulators

Systematic approach for discrete-time to continuous-time transformation of /spl Sigma//spl Delta/ modulators

Figure of merit based design strategy for low-power continuous-time /spl Sigma//spl Delta/ modulators

Efficient time-domain simulation of continuous-time /spl Delta//spl Sigma/ A/D converters using analytical integration

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CMOS R-MOSFET-C fourth-order Bessel filter with accurate group delay

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A silicon model of an adapting motoneuron

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Tonal behavior analysis of an adaptive second-order sigma-delta modulator

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Organic molecules and composites with applications in micro and nanoelectronic systems

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Design rewiring for power minimization [logic design]

Energy dissipation modeling of lossy transmission lines driven by CMOS inverters

Confronting violations of the TSCG(T) in low-power design

Iterative solution of ODE-PDE-AE systems for RF circuit simulation

An efficient low-power binding algorithm in high-level synthesis

JPEG-2000 on an advanced architecture, multiple execution unit DSP

Analysis of EBCOT decoding algorithm and its VLSI implementation for JPEG 2000

JPEG2000 adaptive rate control for embedded systems

A vector based fast block motion estimation algorithm for implementation on SIMD architectures

A hardware accelerator for video segmentation using programmable morphology PE array

Simplified input current waveshaping technique by using inductor voltage sensing for power factor correction isolated Sepic rectifier

Evaluation of an improved input current shaper used as power factor corrector in electronic ballast

A single-phase three-level boost type rectifier

Design considerations in sliding-mode controlled parallel-connected inverters

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Efficient digit-serial FIR filters with skew-tolerant domino

Low power implementation of high throughput FIR filters

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Input isolated sense amplifiers

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Simplified Reed-Muller expressions for residue threshold functions

VLSI realization of four-port ear-type transmission lattice filter

Simple parallel weighted order statistic filter implementations

A study of robustness and coupling-noise immunity on simultaneous data transfer CDMA bus interface

The reduction of sampling noise in switched-capacitor circuits through spatial oversampling

A novel double sampled chopper stabilised integrator for switched capacitor /spl Sigma//spl Delta/ modulators

Approximating linear phase with IIR SC filters

A 3-V 44-MHz switched-capacitor bandpass filter for digital video application

High-selectivity SC filters with continuous digital Q-factor programmability

A 5th order Gm-C filter in 0.25 /spl mu/m CMOS with digitally programmable poles and zeroes

A design of a low-power, high-accuracy, and constant-Q-tuning continuous-time bandpass filter

Application of group delay equalisation in testing fully-balanced OTA-C filters

A general approach to continuous-time G/sub m/-C filters based on matrix descriptions

A low-power 5.4 kHz CMOS gm-C bandpass filter with on-chip center frequency tuning

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Tunable floating-gate low-voltage transconductor

A 2-V 11-bit incremental A/D converter using floating gate technique

Mel-frequency cepstrum encoding in analog floating-gate circuitry

Quadrature mismatch-shaping

Segmented mismatch-shaping D/A conversion

Dynamic element matching in low oversampling delta sigma ADCs

Delta-sigma algorithmic analog-to-digital conversion

Digital correlation technique for the estimation and correction of DAC errors in multibit mash /spl Delta//spl Sigma/ ADCs

Task graph transformation to aid system synthesis

Behavioral synthesis of datapaths with low leakage power

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Optimal circuit clustering with variable interconnect delay

A design methodology for IP integration

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Methods and needs for transcoding MPEG-4 fine granularity scalability video

Reduced spatio-temporal transcoding using an intra refresh technique

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Pole-zero tracking frequency compensation for low dropout regulator

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Buck-boost switched-capacitor DC-DC voltage regulator using delta-sigma control loop

Nominal and tolerance design of closed-loop controllers for DC-DC voltage regulators

Tolerance design of DC-DC switching regulators

A multiplier-less 1-D and 2-D fast Fourier transform-like transformation using sum-of-powers-of-two (SOPOT) coefficients

High-performance FIR generation based on a timing-driven architecture and component selection method

An FPGA implementation of an on-line radix-4 CORDIC 2-D IDCT core

New algorithms for computing the minimum eigenpair of the generalized symmetric eigenvalue problem

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A linear phase detector for arbitrary clock signals

CMOS auto-ranging PLL for low-voltage wideband systems

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A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers

A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scaling

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Analysis of CMOS RF LNAs with ESD protection

A monolithic 2.45 GHz, 0.56 W power amplifier with 45% PAE at 2.4 V in standard 25 GHz f/sub T/ Si-bipolar

A 2 GHz CMOS even harmonic mixer for direct conversion receivers

Gain/phase imbalance and DC offset compensation in quadrature modulators

Finite-length synthesis filters for non-uniformly time-interleaved analog-to-digital converter

A two-pass optimal motion-threading technique for 3D wavelet video coding

Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm

Adaptive wavelet thresholding for time varying SNR signal denoising

Least squares solution of nearly square overdetermined sparse linear systems

A simple simulation method for analyzing substrate coupling

Timing analysis of tree-like RLC circuits

Mutual transformations between Haar wavelet and arithmetic spectra

Incorporation of input glitches into power macromodeling

A coefficient memory addressing scheme for VLSI implementation of FFT processors

Random number generator architecture and VLSI implementation

The two-phase twisted-ring counter circuit

A hierarchy of physical design watermarking schemes for intellectual property protection of IC designs

An adaptive data compression scheme for memory traffic minimization in processor-based systems

CASCADE - configurable and scalable DSP environment

Register-based reordering networks for matrix transpose

Hardware implementation of the SAFER+ encryption algorithm for the Bluetooth system

VLSI architectures for the implementation of the Wigner distribution

Architectural support for detection of sleepy eye behavior

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Tutorial Guide. ISCAS 2001. IEEE International Symposium on Circuits and Systems (Cat. No.01TH8573)

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)

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A design of a low-power, high-accuracy, and constant-Q-tuning continuous-time bandpass filter

Content Provider	IEEE Xplore Digital Library
Author	Pham, T.K. Allen, P.E.
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA (Pham, T.K.; Allen, P.E.)
Abstract	This paper presents a methodology to design low-power continuous-time integrated filters for high-performance wireless applications such as Personal Communication System (PCS), Personal Digital Cellular (PDC), or Wideband Code-Division Multiple Access (WCDMA) handsets. Techniques to enhance the performance of integrated filters by reducing the excess-phase as well as the feature for constant-Q tuning is introduced. In conjunction with the design of a low-power bandpass filter (BPF), a proposal of a high-accuracy and high-speed automatic tuning scheme is also presented. A twelfth-order 450-kHz G/sub m/-C BPF is designed and fabricated using 0.25 /spl mu/m CMOS technology. The BPF consumes 2.4 mA from a 3-V power-supply. The tuning range is from 300 kHz to 675-kHz. The total area-consumption is approximately 2.34 mm/sup 2/.
Sponsorship	IEEE IEEE Circuits & Syst. Soc
File Size	275513
File Format	PDF
ISBN	0780374487
DOI	10.1109/ISCAS.2002.1010537
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Band pass filters Active filters Multiaccess communication CMOS technology Circuit topology Design engineering Design methodology Digital filters Application software Personal communication networks
Content Type	Text
Resource Type	Article

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