NDLI: A New Design Method for VLSI Signal Processors

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[Sessions - Table of Contents]

Block-Oriented Systems Simulator (BOSS)

A Layered Approach to Simulating Communication Systems using Simula

Simulation System Architecture Design for Generic Communications Link

Computer Aided Performance Analysis of Multi-h CPM Data Transmission Systems in Practical Environments

Simulation of Adaptive Antennas in a Spread Spectrum Communications Environment

An Alternate Approach to Digital System Modelling for Computer Simulation

GaAs MMIC Frequency Converters and their System Applications

High Power GaAs FET Solid State Amplifier (32 watt) Development Program

A 32-Bit RISC Implemented in Enhancement-Mode JFET GaAs

Technology Characteristics and Concerns Arising in the Design and Fabrication of an Entire Signal Processor using Gallium Arsenide Integrated Circuits

Circuit Response of GaAs MMICs and Bias Networks to Ionizing Radiation Transients

LSI Gigabit Logic In Silicon (An Alternative to GaAs)

GaAs: Practical Interconnection Design Considerations

A Distributed Binary Tree Protocol with Advanced Reservation (DBTP/AR) for Local Area Networks

Meeting DOD's Requirements - FTAM vs. FTP

A Microcontrolled DMA with a Versatile Linked List Capability for LAN Gateway Applications

Rapid Prototyping using Local Area Network (LAN) Technologies

New Protocols for Tactical Data

Performance of Receivers in Digital Radio Applications Operating in the Presence of Noise and Jamming

Analysis of Generalized Tamed Frequency Modulation with Discriminator Detection in Mobile Radio Channels

Design of a Testbed for Studying Rapidly Reconfigurable Tactical Communication Networks

Proposed Routing Algorithms for the U.S. Army Mobile Subscriber Equipment (MSE) Network

Gateway-to-Gateway Protocol Issues in a Tactical Environment

Probability of Error Analyses of a BFSK-FH System with Diversity Under Partial-Band Multiple Tone Interference

Loss of SNR in Low Pass Filtered FM/MSK

Predicting CNR Frequency Hopping Interference by Simulation

Mutual Interference of QPSK and Spread Spectrum Signals

Frequency Synthesizer Transient Effects in FH-FSK

A Source Representation Space Approach To Eigenstructure Based Broadband Source Location Estimation

Estimation of Multiple Directions

High-Resolution Techniques for Angle-of-Arrival Estimation

A Generalized Approach to Direction Finding

Performance Analysis of the Music Algorithm with Spatial Smoothing in the Presence of Coherent Sources

Estimation of Signal Parameters via Rotational Invariance Techniques - ESPRIT

Simple Method for Designing or Analyzing an Optical Communication Link

A Synchronization Technique for Optical PPM Signals

Word and Frame Synchronization with Verification for PPM Optical Communications

Polarization Effects in Optical Free Space Communications

Airborne Laser Communications Scintillation Measurements

VLSI Design Considerations within Digital Radio

Multiple-Valued Programmable Logic Array with Application to Pipelined Signal Processing

A New Design Method for VLSI Signal Processors

An All Digital Demodulator using Off-the-Shelf VLSI Technology

VLSI Reed Solomon Decoder Design

An Ultra High Speed Optoelectronic Multiplexer Bus as an Integral Design Component for a Parallel Computer

Experimental Results on the Cross-Coupled Phase-Locked Loop Interference Canceller with Closed Loop Amplitude Control

Fixed Point Implementation of Cross Coupled Phase Lock Loops

CMA-based Techniques for Adaptive Interference Rejection

Enhancing Resistance to a Tone Jammer with Preferred Code Segments

Applications of Least-Square Lattice Filters in Adaptive Data Communication

MSE Adaptive Baseband Canceller Performance in Dual-Polarized 16-QAM Systems

On Ccommunication Switching in Tactical and Field Environments

Burst Switching - A New Tactical Switching Concept

Communications Switching Architectures for Integrated Services Applications

Military Interfaces for a Burst Switch

Modular Multi-Microprocessor based Multipoint Communications Network (MCN) Offers Improved Cost/Performance and Future Growth for Today's Terrestrial Critical Control Circuit (TCCC) Networks

An Image Compression System

Quad-Tree based Two Source Image Coding

Matrix Quantization of Homomorphically Processed Images

LSI Architecture for VQ Systolic Array Systems

A Simple Predictive Transform Coder for Images

A Systolic Architecture for Real-Time Composite Video Image Coding

Progress in Underlying Technologies for the Information Age

System Scale Integration for the Nineties an Overview

The AT&T Architecture: Evolving to an Integrated Services Digital Networks

DCTN: An Integrated Services Digital Network for the Department of Defense

Issues in the Migration of Military Communications to an ISDN

Application of ISDN to Interconnect Heterogeneous Switched Networks

Volume 2 - 1986

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A New Design Method for VLSI Signal Processors

Content Provider	IEEE Xplore Digital Library
Author	Haggarty, Ronald D. Johnson, Bruce L. Palo, Edward A.
Copyright Year	1986
Description	Author affiliation: The MITRE Corporation, Burlington Road, Bedford, MA 01730 (Haggarty, Ronald D.; Johnson, Bruce L.; Palo, Edward A.)
Abstract	This paper presents a new method of designing digital signal processors for very large scale integrated (VLSI) circuit implementation with residue number systems (RNS), as opposed to the binary number systems traditionally used. In an RNS, a number is represented by its residues, modulo a set of relatively prime integers. The basic operations of modulo addition and multiplication are simpler in RNS because they can be executed independently in each residue class. Consequently, a desired linear function can be executed in a set of parallel channels on a chip, where each channel performs the same calculation modulo the integer used in that channel. Complexity is thus reduced by two mechanisms. Interconnections between parallel channels are eliminated and all operations are performed modulo the small integer used in each parallel channel of the RNS structure. The square law of circuit complexity applied to this set of small integers results in small, simple circuits. Speed of computation is increased because carry propagation delays are avoided. Further, the RNS design is combined with systolic arrays in such a way that the desired function becomes a parallel set of nearest neighbor-connected identical cells, each of which is minimally complex. The regularity minimizes interconnections and design time -- only one master VLSI macrocell that can be optimized and replicated under computer-aided design (CAD) control is needed.
File Size	2016668
File Format	PDF
DOI	10.1109/MILCOM.1986.4805858
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1986-10-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design methodology Very large scale integration Signal processing Integrated circuit interconnections Design automation Process design Signal design Digital signal processors Complexity theory Propagation delay
Content Type	Text
Resource Type	Article

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