NDLI: Design and implementation of an RSA public-key cryptosystem

Content Provider	IEEE Xplore Digital Library
Author	Jyh-Huei Guo Chin-Liang Wang Hung-Chih Hu
Copyright Year	1999
Description	Author affiliation: Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan (Jyh-Huei Guo)
Abstract	This paper presents a new bit-serial systolic array for realizing a modified Montgomery algorithm for modular multiplication. The proposed array is highly regular, modular, and thus well suited to be implemented using VLSI techniques. It does not involve any broadcasting signals and thus can be operated at a higher clock rate than existing designs. A VLSI architecture for modular exponentiation, which can be used to implement the encryption, decryption, and digital signature of an RSA public-key cryptosystem, is also constructed based on the proposed modular multiplier. For the purpose of verification, a prototype chip of a 512-bit RSA public-key cryptosystem is designed based on the high-performance COMPASS 0.6 /spl mu/m standard cell library. The gate count of the chip is about 132 k and the die size is about 8280 /spl mu/m/spl times/8224.8 /spl mu/m. With an estimated clock rate of 143 MHz, a baud rate of 2781 k bits/sec can be achieved.
Starting Page	504
Ending Page	507
File Size	393822
Page Count	4
File Format	PDF
ISBN	0780354710
DOI	10.1109/ISCAS.1999.777939
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-05-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Public key cryptography Clocks Very large scale integration Systolic arrays Signal design Prototypes Digital signatures Software libraries Data security Authentication
Content Type	Text
Resource Type	Article

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