NDLI: Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity

Content Provider	IEEE Xplore Digital Library
Author	Girard, P. Guiller, L. Landrault, C. Pravossoudovitch, S. Figueras, J. Manich, S. Teixeira, P. Santos, M.
Copyright Year	1999
Description	Author affiliation: CNRS, Montpellier, France (Girard, P.)
Abstract	Low-power design looks for low-energy BIST. This paper considers the problem of minimizing the energy required to test a BISTed combinational circuit without modifying the stuck-at fault coverage and with no extra area or delay overhead over the classical LFSR architectures. The objective of this paper is twofold. First, is to analyze the impact of the polynomial and seed selection of the LFSR used as TPG on the energy consumed by the circuit. It is shown that appropriately selecting the seed of the LFSR can lead to an important energy reduction. Second, is to propose a method to significantly decrease the energy consumption of BIST sessions. For this purpose, a heuristic method based on a simulated annealing algorithm is briefly described in this paper. Experimental results using the ISCAS benchmark circuits are reported, showing variations of the weighted switching activity ranging from 147% to 889% according to the seed selected for the LFSR. Note that these results are always obtained with no loss of stuck-at fault coverage.
Starting Page	110
Ending Page	113
File Size	560162
Page Count	4
File Format	PDF
ISBN	0780354710
DOI	10.1109/ISCAS.1999.777817
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-05-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Circuit testing Circuit faults Combinational circuits Delay Polynomials Energy consumption Circuit simulation Simulated annealing Switching circuits
Content Type	Text
Resource Type	Article

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