NDLI: Design of low power variable length decoder using fine grain non-uniform table partitioning

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Knowledge engineering for analogue design facilitation

Analog circuit sizing with constraint programming modeling and minimax optimization

Efficient noise analysis of ideal switched-capacitor networks with experimental verification

A novel time-frequency method for the simulation of the steady state of circuits driven by multi-tone signals

Analytical estimation of transition activity for DSP architectures

Low power synthesis via transparent latches and observability don't cares

Reducing the size of a BDD in the combinational circuit power estimation by using the dynamic size limit

Power estimation considering statistical IC parametric variations

Estimation of inertial-delay dependent switching activities by using time-stamped transition density

Exploring module selection space for architectural synthesis of low power designs

Low power technology mapping by hiding high-transition paths in invisible edges for LUT-based FPGAs

Design automation algorithms for regenerative pass-transistor logic

Performance improvement of a genetic algorithm for floorplanning with parallel computing technology

Design and implementation of a global router based on a new layout-driven timing model with three poles

Timing-driven pin assignment with improvement of cell placement in standard cell layout

A positioning problem of fictitious terminals for a parallel router based on area division

A new channel pin assignment algorithm and its application to over-the-cell routing

On the Steiner tree problem in L/sub 3/-metric [VLSI wiring]

Fast optimal algorithms for the minimum rectilinear Steiner arborescence problem

A graph-theoretic sufficient condition for FPGA/FPIC switch-module routability

Enhancing schedulability of hard real-time systems through codesign

System level analysis of a coprocessor architecture for block matching motion estimation computation

An architecture evaluation system based on the datapath structure and parallel constraint

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Minimal logic re-synthesis for engineering change

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Reconfiguration of degradable VLSI/WSI arrays under the constraint of row bypass and column rerouting

A current-based model for the MOS transistor

D.C. electrothermal hybrid model of p-n diode for SPICE

Use of the combined-fine-coarse mesh transmission line matrix method for the thermal modelling of integrated circuits

A simulation environment for pipelined analog-to-digital converters

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Circuit modeling of programmable logic gate based on controlled quenching of series-connected negative differential resistance devices

Symbolic analysis in analog integrated circuit design: an application example

Behavioral model of a 1.8 V 6b CMOS flash ADC based on device parameters

Visualization of trade-offs in optimization of integrated circuits with multiple objectives

Mismatch distance term compensation in centroid configurations with nonzero-area devices

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A new optimization cost model for VLSI standard cell placement

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Nonlinear circuit simulation based on adaptive wavelet method

Determination of optimum on-chip bypass capacitor in CMOS VLSI systems to reduce switching noise

Strategies for automatic synthesis of analog building blocks

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Analysis of two dimensional circuits based on multi-conductor theorem

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A suboptimal algorithm of spectrum shaping filter with SAW multistrip coupler

New approaches in randomized preprocessing for motion planning

Comparison of matroid intersection algorithms for large circuit analysis

Use of selective precharge for low-power content-addressable memories

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Discrete-state analysis technique for accurate estimation of switching activities in embedded CMOS combinational circuits

High-level power estimation of VLSI systems

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A low power 100 MHz all digital delay-locked loop

Hierarchical synchronization scheme using self-timed mesochronous interconnections

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A logarithmic photoreceptor incorporating lateral bipolar transistors for improved matching and dynamic range

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Scheduling and optimal voltage selection for low power multi-voltage DSP datapaths

Design of low power variable length decoder using fine grain non-uniform table partitioning

Optimal placement of registers in data paths for low power design

Low-power digit-serial multipliers

Retiming of latches for power reduction of DSP designs

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1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96

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Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

1993 IEEE International Symposium on Circuits and Systems

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems

1991., IEEE International Sympoisum on Circuits and Systems

IEEE International Symposium on Circuits and Systems

IEEE International Symposium on Circuits and Systems,

1988., IEEE International Symposium on Circuits and Systems

Design of low power variable length decoder using fine grain non-uniform table partitioning

Content Provider	IEEE Xplore Digital Library
Author	SeongHwan Cho Xanthopoulos, T. Chandrakasan, A.P.
Copyright Year	1997
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA (SeongHwan Cho)
Abstract	Variable length coding is a widely used technique in digital video compression systems. Previous work related to variable length decoders are primarily aimed at high throughput applications, but the increased demand for portable multimedia systems has made power a very important factor. In this paper a data driven variable length decoding algorithm is presented, which exploits the signal statistics of variable length codes to reduce power. It uses fine grain lookup table partitioning based on codeword frequency. An order magnitude of power reduction is possible compared to conventional parallel decoding scheme with a single lookup table.
Starting Page	2156
Ending Page	2159
File Size	383715
Page Count	4
File Format	PDF
ISBN	078033583X
DOI	10.1109/ISCAS.1997.621597
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-06-12
Publisher Place	Hong Kong
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Table lookup Detectors Statistics Binary trees Equations Video compression Throughput Partitioning algorithms Frequency
Content Type	Text
Resource Type	Article

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