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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Gi-Hong Im Shanbhag, N.R. |
| Copyright Year | 1997 |
| Description | Author affiliation: AT&T Bell Labs., Middletown, NJ, USA (Gi-Hong Im) |
| Abstract | Presented in this paper are: (1) system design issues for the implementation of 51.84 Mb/s ATM-LAN transceivers, (2) an integrated VLSI design methodology underlying this design, and (3) a pipelined fractionally-spaced linear equalizer (FSLE) architecture. The integrated design methodology incorporates algorithmic concerns such as signal-to-noise ratio (SNR) and bit-error rate (BER) along with VLSI constraints such as power dissipation, area, and speed, within a common framework. Characteristics of the channel and the modulation scheme are described. An adaptive FSLE, employed in the receiver, eliminates ISI, suppresses NEXT (in case of ATM-LAN) and provides robustness to timing jitter. A pipelined FSLE architecture is derived via the relaxed look-ahead technique for high-sample rate adaptation. Simulation and experimental results for high-speed digital CAP transceivers for LAN are also presented. |
| Starting Page | 2128 |
| Ending Page | 2131 |
| File Size | 405574 |
| Page Count | 4 |
| File Format | |
| ISBN | 078033583X |
| DOI | 10.1109/ISCAS.1997.621590 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1997-06-12 |
| Publisher Place | Hong Kong |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Very large scale integration Design methodology Transceivers Bit error rate Equalizers Signal to noise ratio Power dissipation Intersymbol interference Robustness Timing jitter |
| Content Type | Text |
| Resource Type | Article |
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