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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Friedman, V. |
| Copyright Year | 1997 |
| Description | Author affiliation: NJ Design Center, Analog Devices Inc., Somerset, NJ, USA (Friedman, V.) |
| Abstract | For high speed digital communications VLSI signal processors such as those used in VDSL and ATM LAN applications, the logic associated with the feed-forward equalizer taps accounts for much of the silicon area and power dissipation. The paper presents a novel arithmetic unit, which allows one to reduce the size of the multipliers. One of the multiplicands, the data, is stored in fixed point format, while the other, the error (coefficient) is converted in floating point format with a reduced mantissa width. In the case of the error, the coefficient update multiplier can be replaced with a shift and add structure. For the equalizer FIR section, the coefficients are split in sets and the coefficient mantissa width is optimized for each set. This procedure allows one to minimize the quantization noise for a given total coefficient length. |
| Starting Page | 2124 |
| Ending Page | 2127 |
| File Size | 292682 |
| Page Count | 4 |
| File Format | |
| ISBN | 078033583X |
| DOI | 10.1109/ISCAS.1997.621589 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1997-06-12 |
| Publisher Place | Hong Kong |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Equalizers Digital communication Very large scale integration Signal processing Local area networks Logic Feedforward systems Silicon Power dissipation Arithmetic |
| Content Type | Text |
| Resource Type | Article |
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