NDLI: Semi-automatic development of test program sets (TPS)

Content Provider	IEEE Xplore Digital Library
Author	Berk, K. Flann, N. Howell, C. Wille, K.
Copyright Year	2003
Description	Author affiliation: Total Quality Syst. Inc., Ogden, UT, USA (Berk, K.; Flann, N.; Howell, C.; Wille, K.)
Abstract	This paper describes the research and development of methods and processes to automate the generation of adaptable test programs, from functional specifications, that will reduce the cost and time required to establish an organic depot test and repair capability. With increasing emphasis on performance based acquisition (PBA) throughout the DoD and USAF, this technology is essential. The prototype being described in this paper starts with a functional model of the circuit. Possible faults are automatically generated, and then the modified circuits are simulated to create training data for a set of neural networks. The new TPS consists of a series of trained neural networks that automatically identify failed component groups or determine no-fault in the actual units under test (UUT). The technology being developed in this effort compliments ongoing PBA activity to improve reliability and reduce the cost of sustaining avionics systems by reducing test results of no fault found. This paper shows the integration of neural network technologies with software and hardware modeling to develop innovative, adaptive and effective diagnostic test programs.
Sponsorship	IEEE Aerosp. & Electron. Syst. Soc. IEEE Instrumentation & Meas. Soc. IEEE LEOS Angeles Council IEEE Orange County Sect
Starting Page	217
Ending Page	225
File Size	571967
Page Count	9
File Format	PDF
ISBN	0780378377
ISSN	10807725
DOI	10.1109/AUTEST.2003.1243581
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-09-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic testing Neural networks Circuit testing Circuit faults Research and development Cost function Prototypes Circuit simulation Training data Aerospace electronics
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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