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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chingwei Yeh Chi-Shong Wang |
| Copyright Year | 2000 |
| Description | Author affiliation: Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chia-Yi, Taiwan (Chingwei Yeh) |
| Abstract | RISC architecture plays a major role in recent embedded systems design. The notorious drawback of a RISC machine is its poor code density. Many research works have been proposed to reduce the code density. However, they either need a sophisticated compression-decompression mechanism, or are suitable for specific applications. In this paper, a method to compress a post-compilation program is proposed to improve code density while introducing minimal hardware overhead. The salient features of our technique are: (1) the decompression circuitry depends only on the instruction set of a processor and so is reusable for any application running on the same processor; and (2) there is no limitation on the size of the program to be compressed. We demonstrate our technique on SPEC CINT95 benchmark programs using the ARM7TDMI instruction set and achieve an average code size reduction of 19.8%. |
| Starting Page | 226 |
| Ending Page | 230 |
| File Size | 504104 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780365984 |
| DOI | 10.1109/ASIC.2000.880706 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2000-09-16 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Reduced instruction set computing Embedded system Hardware Energy consumption Costs System-on-a-chip Circuits Modems TV Control systems |
| Content Type | Text |
| Resource Type | Article |
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