NDLI: Design and synthesis of built-in self-testable two-dimensional discrete cosine transform circuits

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15th Annual IEEE International ASIC/SOC Conference

Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)

Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)

Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)

Design and synthesis of built-in self-testable two-dimensional discrete cosine transform circuits

Switched-current filter design for image processing systems

A reconfigurable pipelined IDCT for low-energy video processing

Fast digital photon correlation system with high dynamic range

Obeying Moore's law beyond 0.18 micron [microprocessor design]

The ideal SoC memory: 1T-SRAM/sup TM/

An 0.18 /spl mu/m embedded FCRAM ASIC with DRAM density and SRAM performance

High-speed adder design using time borrowing and early carry propagation

Interpolation-based digital quadrature frequency synthesizer

On-chip /spl Delta/I noise in the power distribution networks of high speed CMOS integrated circuits

A system-level simulation environment for system-on-chip design

A QAM modulator for WCDMA base station

A DFE equalizer ASIC chip using the MMA algorithm

Vector quantization processor for mobile video communication

VLSI implementation of portable MPEG-4 audio decoder

A parametrizable hybrid stack-register processor as soft intellectual property module

Hipar-DSP-a scalable family of high performance DSP-cores

Improved VLSI designs for multiplication and inversion in GF(2/sup M/) over normal bases

ICORE: a low-power application specific instruction set processor for DVB-T acquisition and tracking

Direct-conversion quadrature-modulator for 0.8-GHz with flip-chip passives [BiCMOS RF IC]

Optimization of a 0.13 /spl mu/m CMOS backend interconnect process for ASIC SOC: low K dielectric vs. Cu conductor

An efficient method for estimating switching activity in arithmetic circuits using a lumped delay model

Blind estimation and error correction in a CMOS ADC

IVE: an Internet based distributed VHDL environment

Low level watermarking of VLSI designs for intellectual property protection

Robust mobile computing-a case study in architecture performance evaluation

SOC-driven design methodology for full custom high performance mixed-signal designs

Coware pipelining for exploiting intellectual properties and software codes in processor-based designs

Architechture level optimization for asynchronous IPs

Designing reusable components in VHDL

A layered approach to behavioral modeling of bus protocols

High-level synthesis and behavioral VHDL writing style towards a methodology for behavioral IP reuse

Design, optimization, and implementation of a universal FFT processor

Methodology and code reuse in the verification of telecommunication SOCs

Development and application of a macro model for flash EEPROM design

CD-ROM drive system

An embedded PowerPC/sup TM/ SOC for test and measurement applications

A mixed-mode single-chip motor-drive-specific microcontroller with a 12-bit 125/KS/s ADC

A 64/256 QAM receiver chip for high-speed communications

An energy-efficient leakage-tolerant dynamic circuit technique

A program compression technique supporting IP-centric SOC design

Low-power 4-way associative cache for embedded SOC design

Digit-serial fixed coefficient complex number multiplier-accumulator on FPGAs

Low power VLSI prototype for motion tracking architecture

Design self-synchronized clock distribution networks in an SoC ASIC using DLL with remote clock feedback

Using computational RAM for volume rendering

Modeling energy of the clock generation and distribution circuitry

Orthogonal partitioning and gated clock architecture for low power realization of FSMs

A complete model for glitch analysis in logic circuits

POPS: A tool for delay/power performance optimization

Design of databus charge recovery mechanism

On-chip decoupling capacitor optimization using architectural level current signature prediction

Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits

High level estimation of the area and power consumption of on-chip interconnects

Power optimization of delay constrained circuits

Low-power skewed static logic (S/sup 2/L) with topology-dependent dual Vt

Power optimization of standard cell flip flops

Characterization of interconnect coupling noise using in-situ delay-change curve measurements

A differential high-speed digital CMOS buffer with hysteresis for improved noise immunity

Capturing input switching dependency in crosstalk noise modeling

Efficient static timing analysis in presence of crosstalk

An effective modeling technique for the delay calculation and the skew analysis of clock grid designs

Model reductions in MDG-based model checking

Formal representation of gated clock designs

Dynamic-threshold CMOS SRAM cells for fast, portable applications

A zero-overhead self-timed divider using new pipeline scheme

Scalable binary sorting architecture based on rank ordering with linear area-time complexity

High throughput FIR filter design for low power SoC applications

Low power controller optimization based on data path pattern extraction

RightTopologizer: an efficient schematic generator for multi-level optimization

Coupling aware routing

Real time application architectural synthesis dedicated to sub-micron technologies

Cell library development using multi-objective function optimization

Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454)

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in