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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hoon Choi In-Cheol Park |
| Copyright Year | 2000 |
| Description | Author affiliation: Syst. LS, Samsung Electron., South Korea (Hoon Choi) |
| Abstract | Growing requirements on the correct design of high-performance systems in a short time force us to use IP's in many designs. In this paper, we propose a pipelining technique, called coware pipelining, to efficiently use IP's in ASIP designs such that the application program meets the performance constraints with minimum cost. The coware pipelining is an extended version of the software pipelining to take into account IP's and software codes simultaneously. The proposed approach can increase parallelism among tasks significantly over the original one and can lead to better use of IP's, while the previous state-of-the-art approaches can exploit only the original parallelism represented in the application program. The experimental results on real applications show the efficiency of the proposed method in exploiting IP's. |
| Starting Page | 153 |
| Ending Page | 157 |
| File Size | 527069 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780365984 |
| DOI | 10.1109/ASIC.2000.880693 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2000-09-16 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Pipeline processing Application specific processors Costs Hardware Process design Acceleration Application software Computer architecture Software performance Large scale integration |
| Content Type | Text |
| Resource Type | Article |
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