NDLI: Analysis and design of a 30 MHz resonant SEPIC converter

Content Provider	IEEE Xplore Digital Library
Author	Jingya Lin Yuan Zhou Zhiliang Zhang Xinbo Ruan Yan-Fei Liu
Copyright Year	2015
Description	Author affiliation: Jiangsu Key Lab. of New Energy Generation & Power Conversion, Nanjing Univ. of Aeronaut. & Astronaut., Nanjing, China (Jingya Lin; Yuan Zhou; Zhiliang Zhang; Xinbo Ruan) \|\| Dept. of Electr. & Comput. Eng., Queen's Univ., Kingston, ON, Canada (Yan-Fei Liu)
Abstract	This paper presents the analysis and design of a resonant SEPIC converter operating at 30 MHz. With the conventional design method, tuning the amplitude and phase of the fundamental input voltage and current affect each other so that the design procedure is trial-and-error. An improved design method is proposed by re-dividing the resonant SEPIC topology and defining the new variables to realize the independent tuning of the amplitude and phase. The loss analysis is provided. A 15 V input, 14 W/28 V output, 30 MHz prototype has been built to verify the proposed design method. The prototype achieves the efficiency above 80% over a wide load. Furthermore, a novel structure of the PCB embedded inductors is used in a 25 W prototype to further improve the power density.
Starting Page	455
Ending Page	460
File Size	2156842
Page Count	6
File Format	PDF
ISBN	9781479967353
DOI	10.1109/APEC.2015.7104390
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-03-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Rectifiers Inductors Design methodology Topology Inverters MOSFET Resistance PCB inductor VHF SEPIC design method
Content Type	Text
Resource Type	Article

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