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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Roig, J. Tong, C.-F. Bauwens, F. Gillon, R. Massie, H. Hoggatt, C. |
| Copyright Year | 2014 |
| Description | Author affiliation: ON Semicond., Oudenaarde, Belgium (Roig, J.; Tong, C.-F.; Bauwens, F.; Gillon, R.) || ON Semicond., Phoenix, AZ, USA (Massie, H.; Hoggatt, C.) |
| Abstract | The impact of the shield resistance (Rsh) on the waveform ringing and system efficiency is assessed in this work for 30V trench power FETs with shielded-gate (TP-FETs). Two different approaches, named distributed and local Rsh, are extensively investigated by experimental and numerical simulation tools. A layout distributed Rsh emerges as the ultimate solution to maximize the self-damping without penalization on the switching power losses or the product cost. The practical implementation of a TP-FET with distributed Rsh in a 12V-to-1.2V buck converter results in one of the best tradeoffs ever reported between overvoltage (<;3.5V) and peak efficiency (~88%) when operating at 1.3MHz. |
| Sponsorship | IEEE Power Electron. Soc. |
| Starting Page | 137 |
| Ending Page | 142 |
| File Size | 1333493 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781479923250 |
| DOI | 10.1109/APEC.2014.6803300 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-03-16 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Field effect transistors Snubbers Resistance Layout Capacitance Metals |
| Content Type | Text |
| Resource Type | Article |
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