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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Scharrer, M. Halton, M. Scanlan, T. Rinne, K. |
| Copyright Year | 2010 |
| Description | Author affiliation: Dept. Electronic and Computer Engineering, University of Limerick Limerick, Ireland (Scharrer, M.; Halton, M.; Scanlan, T.; Rinne, K.) |
| Abstract | This paper proposes a new FPGA-based architecture for a multi-phase digital pulse width modulator (MP-DPWM). A novel fine-leading/coarse-trailing edge modulation is applied to allow the sharing of a single fine resolution block for all phases. Specifically, the architecture takes advantage of Digital Clock Manager (DCM) blocks available in modern FPGAs to produce four clock phases from a single clock input to increase the resolution by two bit. An optimized counter/shift-register block is detailed which reduces the size and increases the maximum clock frequency of the architecture for certain numbers of phases. The design was successfully implemented on a low-cost Xilinx Spartan-3 FPGA 9-bit resolution with a switching frequency of 1 MHz and 2–16 phases. |
| Starting Page | 1075 |
| Ending Page | 1080 |
| File Size | 518090 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424447824 |
| ISSN | 10482334 |
| DOI | 10.1109/APEC.2010.5433371 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-02-21 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Pulse width modulation Digital modulation Space vector pulse width modulation Clocks Field programmable gate arrays Signal resolution Counting circuits Phased arrays Switched-mode power supply Pulsed power supplies |
| Content Type | Text |
| Resource Type | Article |
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